Bubble Partitioning for LUT-Based Sequential Circuits
In this paper, we present an incremental clustering technique for LUT-based sequential circuits targetting a delay-optimized partitioning of the LUT and latch blocks for FPGA placement. Our cost function considers a slack-based relative delay criticality of circuit nets. As partitions are being constructed simultaneously, the method is open also for further evaluation criteria, e.g. in respect of placeability or routability.
KeywordsCritical Path Target Node Successor Node Sequential Circuit Benchmark Circuit
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