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Bubble Partitioning for LUT-Based Sequential Circuits

  • Frank Wolz
  • Reiner Kolla
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

In this paper, we present an incremental clustering technique for LUT-based sequential circuits targetting a delay-optimized partitioning of the LUT and latch blocks for FPGA placement. Our cost function considers a slack-based relative delay criticality of circuit nets. As partitions are being constructed simultaneously, the method is open also for further evaluation criteria, e.g. in respect of placeability or routability.

Keywords

Critical Path Target Node Successor Node Sequential Circuit Benchmark Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Frank Wolz
  • Reiner Kolla
    • 1
  1. 1.Lehrstuhl für Technische InformatikUniversität WürzburgGermany

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