Bubble Partitioning for LUT-Based Sequential Circuits

  • Frank Wolz
  • Reiner Kolla
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


In this paper, we present an incremental clustering technique for LUT-based sequential circuits targetting a delay-optimized partitioning of the LUT and latch blocks for FPGA placement. Our cost function considers a slack-based relative delay criticality of circuit nets. As partitions are being constructed simultaneously, the method is open also for further evaluation criteria, e.g. in respect of placeability or routability.


Critical Path Target Node Successor Node Sequential Circuit Benchmark Circuit 
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  1. [AY95]
    C. J. Alpert and S. Z. Yao: Spectral Partitioning: The More Eigenvectors, the Better, Proceedings of the 32nd Design Automation Conference, pp. 195–200, 1995Google Scholar
  2. [BR97]
    Vaughn Betz and Jonathan Rose: VPR: A New Packing, Placement and Routing Tool for FPGA Research, 7th Int’l Workshop for Field-Programmable Logic and Applications, LNCS 1304, pp. 213–222, 1997Google Scholar
  3. [FM82]
    C. M. Fiduccia and R. M. Mattheyses: A linear time heuristic for improving network partitions, Proc. of the 19th Design Automation Conference, pp. 175–181, 1982Google Scholar
  4. [GJ79]
    Michael R. Garey, David S. Johnson: Computers and Intractability: A Guide to NP-Completeness, Freeman, New York, p. 209, 1979zbMATHGoogle Scholar
  5. [KAS97]
    Helena Krupnova, Ali Abbara, Gabriele Saucier: A Hierarchy-Driven FPGA Partitioning Method, Proceedings of the 34th Design Automation Conference, pp. 522–525, 1997Google Scholar
  6. [KGV83]
    S. Kirkpatrick, C. D. Gelatt Jr. and M. P. Vecchi: Optimization by simulated annealing, Science, 220(4598), pp. 671–680, 1983CrossRefMathSciNetGoogle Scholar
  7. [KL70]
    B. W. Kernighan and S. Lin: An efficient heuristic procedure for partitioning graphs, Bell Systems Technical Journal, pp. 291–307, Vol. 49, No. 2, 1970Google Scholar
  8. [LZW98]
    Huiqun Liu, Kai Zhu, D.F. Wong: Circuit Partitioning with Complex Resource Constraints in FPGAs, International Symposium on Field-Programmable Gate Arrays, pp. 77–84, 1998Google Scholar
  9. [MBR99]
    Alexander (Sandy) Marquardt, Vaughn Betz and Jonathan Rose: Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density, International Symposium on Field-Programmable Gate Arrays, pp. 37–46, 1999Google Scholar
  10. [MS86]
    D. W. Matula and F. Shahrokhi: Graph partitioning by sparse cuts and maximum concurrent flow, Technical Report, Southern Methodist University, Dallas, TX, 1986Google Scholar
  11. [SIS92]
    Ellen M. Sentovich, Kanwar Jit Singh, et al.: SIS: A System for Sequential Circuit Synthesis,, 1992
  12. [WC89]
    Yen-Chuen Wei and Chung-Kuan Cheng: Towards Efficient Hierarchical Designs by Ratio Cut Partitioning, Proceedings of the International Conference on Computer-Aided Design, pp. 298–301, 1989Google Scholar
  13. [WC91]
    Yen-Chuen Wei and Chung-Kuan Cheng: A General Purpose Multiple Way Partitioning Algorithm, Proceedings of the 28th Design Automation Conference, pp. 421–426, 1991Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Frank Wolz
  • Reiner Kolla
    • 1
  1. 1.Lehrstuhl für Technische InformatikUniversität WürzburgGermany

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