Run-Time Optimized Reconfiguration Using Instruction Forecasting

  • Marios Iliopoulos
  • Theodore Antonakopoulos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


The extensive use of reconfigurable computing devices has imposed a new category of processors, the dynamic instruction set processors (DISPs) that customize their instruction sets dynamically to the application needs. One of the major drawbacks of DISPs is the reconfiguration time needed to alter the instruction set, which is directly added to the program execution time discouraging the use of DISPs especially for time critical processing applications. This paper introduces a methodology for optimizing reconfiguration time through instruction forecasting and presents the results obtained when applying this method to Medium Access processing systems that execute time critical network tasks.


Instruction Cache Dataflow Graph Partial Reconfiguration Reconfiguration Time DISP System 
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  1. 1.
    Michael J. Wirthlin, Improving Functional Density Through Run-Time Circuit Reconfiguration, Ph.D. thesis, 1997.Google Scholar
  2. 2.
    Xilinx, Application Note: Virtex Series Configuration Architecture User Guide, Virtex Series, XAPP151, v1.3, February 2000.Google Scholar
  3. 3.
    Atmel, AT40K05/10/20/40 FPGAs with DSP Optimized Core Cell and Distributed FreeRam, Datasheet, rev. 0896B-01/99, January 1999.Google Scholar
  4. 4.
    E. Tau, I. Eslick, D. Chen, J. Brown, and A. DeHon. A first generation DPGA implementation, Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pages 138–143, May 1995.Google Scholar
  5. 5.
    Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong. A time-multiplexed FPGA. In J. Arnold and K. L. Pocek, editors, Proceedings of the 5th IEEE Symposium on FPGAs for Custom Computing Machines, pages 22–28, Napa, CA, April 1997.Google Scholar
  6. 6.
    M.J. Wirthlin, and B.L. Hutchings, A Dynamic Instruction Set Computer, Proceedings of the 3rd IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 1995, pp. 99–107.Google Scholar
  7. 7.
    Iliopoulos, M., Antonakopoulos, T., Optimized Reconfigurable MAC Processor Architecture, IEEE International Conference on Electronics and Computer Systems (ICECS), Malta, 2001.Google Scholar
  8. 8.
    S. Hauck, Z. Li, and E. J. Schwabe. Configuration Compression for the Xilinx XC6200 FPGA, Proceedings of the 6th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 1998.Google Scholar
  9. 9.
    Iliopoulos, M., Antonakopoulos, T., A Methodology of Implementing Medium Access Protocols Using a General Parameterized Architecture, 11th IEEE International Workshop on Rapid System Prototyping (RSP), June 2000, Paris, FranceGoogle Scholar
  10. 10.
    Iliopoulos, M., Antonakopoulos, T., Reconfigurable Network Processors based on Field Programmable System Level Integrated Circuits, 10th International Conference on Field Programmable Logic and Applications (FPL), Villach, Austria, August 2000.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Marios Iliopoulos
    • 1
    • 2
  • Theodore Antonakopoulos
    • 1
    • 2
  1. 1.Computers Technology Institute (CTT)PatrasGreece
  2. 2.Department of Electrical Engineering and Computers TechnologyUniversity of PatrasPatrasGreece

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