The MOLEN ρμ-Coded Processor

  • Stamatis Vassiliadis
  • Stephan Wong
  • Sorin Cotöfană
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


In this paper, we introduce the MOLEN ρμ-coded processor which comprises hardwired and microcoded reconfigurable units. At the expense of three new instructions, the proposed mechanisms allow instructions, entire pieces of code, or their combination to execute in a reconfigurable manner. The reconfiguration of the hardware and the execution on the reconfigured hardware are performed by ρ-microcode (an extension of the classical microcode to allow reconfiguration capabilities). We include fixed and pageable microcode hardware features to extend the flexibility and improve the performance. The scheme allows partial reconfiguration and includes caching mechanisms for non-frequently used reconfiguration and execution microcode. Using simulations, we establish the performance potential of the proposed processor assuming the JPEG and MPEG-2 benchmarks, the ALTERA APEX20K boards for the implementation, and a hardwired superscalar processor. After implementation, cycle time estimations and normalization, our simulations indicate that the execution cycles of the superscalar machine can be reduced by 30% for the JPEG benchmark and by 32% for the MPEG-2 benchmark using the proposed processor organization.


Clock Cycle Host Processor Execution Cycle MIPS Processor Entire Piece 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    J. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor,” in Proceedings of the IEEE Symposium of Field-Programmable Custom Computing Machines, pp. 24–33, April 1997.Google Scholar
  2. [2]
    J. M. Rabaey, “Reconfigurable Computing: The Solution to Low Power Programmable DSP,” in Proceedings 1997ICASSP Conference, (Munich), April 1997.Google Scholar
  3. [3]
    D. C. Burger and T. M. Austin, “The SimpleScalar Tool Set, Version 2.0,” Technical Report CS-TR-1997-1342, University of Wisconsin-Madison, 1997.Google Scholar
  4. [4]
    “Virtex-II 1.5V FPGA Family: Detailed Functional Description.”
  5. [5]
    C. Loeffler, A. Ligtenberg, and G. Moschytz, “Practical Fast 1-D DCT Algorithms With 11 Multiplications,” in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, pp. 988–991, 1989.Google Scholar
  6. [6]
    R. Razdan, PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, Cambridge, Massachusetts, May 1994.Google Scholar
  7. [7]
    S. A. Hauck, “Configuration Prefetch for Single Context Reconfigurable Coprocessors,” in 6th Int. Symposium on Field Programmable Gate Arrays, pp. 65–74, February 1998.Google Scholar
  8. [8]
    R. D. Wittig and P. Chow, “OneChip: An FPGA Processor With Reconfigurable Logic,” in IEEE Symposium on FPGAsfor Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa Valley, California), pp. 126–135, April 1996.Google Scholar
  9. [9]
    S. M. Trimberger, “Reprogrammable Instruction Set Accelerator.” U.S. Patent No. 5,737,631, April 1998.Google Scholar
  10. [10]
    J. R. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor,” in IEEE Symposium on FPGAs for Custom Computing Machines, (Napa Valley, California), pp. 12–21, April 1997.Google Scholar
  11. [11]
    P. M. Athanas and H. F. Silverman, “Processor Reconfiguration through Instruction-Set Metamorphosis,” IEEE Computer, vol. 26, pp. 11–18, March 1993.Google Scholar
  12. [12]
    K. L. Gilson, “Integrated Circuit Computing Device Comprising a Dynamically Configurable Gate Array Having a Reconfigurable Execution Means.” WO Patent No. 94/14123, June 1994.Google Scholar
  13. [13]
    H. Schmit, “Incremental Reconfiguration for Pipelined Applications,” in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 47–55, April 1997.Google Scholar
  14. [14]
    S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration,” in The 26th International Symposium on Computer Architecture, (Atlanta, Georgia), pp. 28–39, May 1999.Google Scholar
  15. [15]
    R. W. Hartenstein, R. Kress, and H. Reinig, “A New FPGA Architecture for Word-Oriented Datapaths,” in Proceeding of the 4th International Workshop on Field-Programmable Logic and Applications: Architectures, Synthesis and Applications., pp. 144–155, September 1994.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Stamatis Vassiliadis
    • 1
  • Stephan Wong
    • 1
  • Sorin Cotöfană
    • 1
  1. 1.Computer Engineering Laboratory,Electrical Engineering Department,Faculty of Information Technology and SystemsDelft University of TechnologyDelftThe Netherlands

Personalised recommendations