Advertisement

Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays

  • John Karro
  • James Cohoon
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation of this method: Gambit. Based on a graph coloring representation of the routing problem, we are able to produce circuit placements and detailed routes simultaneously, allowing routing constraints to influence decisions made in creating the placement. Gambit produces circuit mappings for both standard and three-dimensional FPGA architectures, and serves primarily as a proofof-concept: the proposed algorithm will simultaneously perform placement and detailed routing for channel-based architectures. While the quality of Gambit mappings are not yet competitive with state-of-the-art tools in the literature, experimental results indicate that it does have the potential to become so.

Keywords

Chromatic Number Virtual Node Logic Block FPGA Architecture Partition Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Aho, A.V., Sethi, R., and Jeffery, U.D. Compilers: Principles, Techniques, and Tools. Addison-Wesley Publishing Company, 1986.Google Scholar
  2. [2]
    Alexander, M.J., Cohoon, J.P., Ganley, J.L., and Robins, G. Performance-oriented placement and routing for field-programmable gate arrays. Proceedings of the European Design Automation Conference, pages 80–85, 1995.Google Scholar
  3. [3]
    Alexander, M.J. and Robins, G. New Performance-Driven FPGA Routing Algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(12):1505–1517, December 1996.Google Scholar
  4. [4]
    Bapat, S. and Cohoon, J.P. A parallel VLSI circuit layout methodology. Proceedings of Sixth International Conference on VLSI Design, pages 236–241, 1993.Google Scholar
  5. [5]
    Betz, V. and Rose, J. VPR: A New Packing, Placement and Routing Tool for FPGA Research. International Workshop on Field Programmable Logic and Applications, pages 213–222, 1997.Google Scholar
  6. [6]
    D. Brelaz. New methods to color the vertices of a graph. Communications of the ACM, pages 251–256, 1979.Google Scholar
  7. [7]
    Karro, J. and Cohoon, J. A Spiffy Tool for the Simultaneous Placement and Global Routing of Three-Dimensional Field Programmable Gate Arrays. Ninth Great Lakes Symposium on VLSI, pages 226–227, March 1999.Google Scholar
  8. [8]
    Lee, Y. and Wu, A. A performance and routability driven router for FPGA considering path delays. Proceedings of the 32 IEEE/ACM Conference on Design Automation, pages 557–561, 1995.Google Scholar
  9. [9]
    Lesser, M., Meleis, W.M., Vai, M.M., and Zavracky, P.M. Rothko: A Three Dimensional FPGA Architecture, Its Fabrication, and Design Tools. Field-Programmable Logic and Applications, 1997.Google Scholar
  10. [10]
    Nag, S.K. and Rutenbar, R.A. Performance-driven simultaneous place and route for FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(5):499–518, June 1998.Google Scholar
  11. [11]
    Nakatake, S., Sakanushi, K., Kajitani, Y., and Kawakita, M. The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. IEEE/ACM International Conference on Computer-Aided Design, pages 418–25, 1998.Google Scholar
  12. [12]
    Rose, J. Parallel Global Routing for Standard Cells. IEEE Transactions on Computer Aided Design, pages 1085–1095, October 1990.Google Scholar
  13. [13]
    Wu, Y.L. and Marek-Sadowska, M. Orthogonal Greedy Coupling-A New Optimization Approach to 2-D FPGA Routing. Proceedings of the ACM/IEEE Design Automation Conference, pages 568–573, 1995.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • John Karro
    • 1
  • James Cohoon
    • 2
  1. 1.Computer Science ProgramOberlin CollegeOberlin
  2. 2.Department of Computer ScienceUniversity of VirginiaCharlottesville, VA

Personalised recommendations