Tightly Integrated Placement and Routing for FPGAs

  • Parivallal Kannan
  • Dinesh Bhatia
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


With increasing FPGA device capacity and design sizes, physical design closure is becoming more difficult, usually requiring multiple lengthy cycles of placement and routing. Increasing demands are being placed upon the placement method to produce routable solutions. Existing FPGA physical design methodologies treat placement and routing as two distinct steps resulting in significant loss of quality and increased design times. A tighter integration between placement and routing is expected to reduce the overall physical design time and produce better quality solutions. This paper presents a new methodology for tightly integrated placement and routing for FPGAs. It provides the capability to introduce the routing concepts to the placement stage itself, ensuring the placement is routability driven and that desired good routes exist for all nets, in the routing stage. This methodology has been implemented for XC6200 family of FPGAs, but can be used with any FPGA architecture.


Simulated Annealing Field Programmable Gate Array Placement Problem Physical Design Logic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Parivallal Kannan
    • 1
  • Dinesh Bhatia
    • 1
  1. 1.Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer ScienceUniversity of Texas at DallasRichardsonUSA

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