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Implementation of a NURBS to Bézier Conversor with Constant Latency

  • Paula N. Mallón
  • Montserrat Bóo
  • Javier D. Bruguera
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

In this paper, a FPGA implementation is presented to carry out the conversion process from NURBS to Bézier curves. It has a simple and regular timing schedule with a constant latency which reduces the area requirements with respect to previous implementations. The operation frequency obtained with the Xilinx tools, is around 13 MHz. The scheme we propose can be easily extended to process NURBS and Bézier surfaces.

Keywords

Control Point NURBS Curve FPGA Implementation FIFO Queue Direct Point 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Mallón, P. N., Bóo, M., Bruguera, J.D.: Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. Proc. Int. Conf. Euromicro 2000. Workshop on Digital Systems Design. DSD2000 (2000) 324–331Google Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Paula N. Mallón
    • 1
  • Montserrat Bóo
    • 1
  • Javier D. Bruguera
    • 1
  1. 1.Department of Electronic and Computer EngineeringUniversity of Santiago de CompostelaSpain

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