Configuration Caching and Swapping

  • Suraj Sudhir
  • Suman Nath
  • Seth Copen Goldstein
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconfiguration. In this paper we compare several new configuration caching algorithms that reduce the latency of reconfiguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the configurations is reduced, lowering the configurable overhead.


Cache Size Virtual Memory Cache Replacement Replacement Algorithm Total Latency 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Suraj Sudhir
    • 1
  • Suman Nath
    • 1
  • Seth Copen Goldstein
    • 1
  1. 1.Carnegie Mellon UniversityUSA

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