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Prototyping Framework for Reconfigurable Processors

  • Sergej Sawitzki
  • Steffen Köhler
  • Rainer G. Spallek
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

During the last decade it has been shown that reconfigurable computing systems are able to compete with their non-reconfigurable counterparts in terms of performance, functional density or power dissipation. A couple of concept and prototyping studies have introduced the reconfigurability within general purpose microprocessor world. This paper introduces a prototyping environment for the design of simple reconfigurable microprocessors. The work differs from the previous approaches in the fact that a systematical way (concerning both hardware and software sides) to design, test and debug a class of reconfigurable computing cores instead of one particular application is discussed. First experiments with a simple 8 bit prototype have shown that the reconfiguration allows performance gains by a factor 2-28 for different applications. The study has discovered some directions for further architectural improvements.

Keywords

Digital Signal Processor Processor Core Program Counter Logic Resource Instruction Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    G. Estrin. Organization of computer systems: The fixed plus variable structure computer. In Proceedings of the Western Joint Computer Conference, pages 33–40, New York, 1960. American Institute of Electrical Engineers.Google Scholar
  2. 2.
    S. A. Guccione. List of FPGA-based computing machines. http://www.io.com/~guccione/HW-list.html, Last Update March 1999, 1999.
  3. 3.
    M. Wirthlin, B. Hutchings, and K. Gilson. The Nano processor: A low resource reconfigurable processor. In D. Buell and K. Pocek, editors, Proceedings of FCCM’94, pages 23–30, Napa, CA, April 1994. IEEE.Google Scholar
  4. 4.
    C. Iseli. Spyder: A Reconfigurable Processor Development System. PhD thesis, Département d’Informatique, École Polytechnique de Lausanne, 1996.Google Scholar
  5. 5.
    R. Razdan. PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, Cambridge, Massachusetts, May 1994.Google Scholar
  6. 6.
    J. Hauser and J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. In J. Arnold and K. Pocek, editors, Proceedings of FCCM’97, pages 24–33, Napa, CA, April 1997. IEEE.Google Scholar
  7. 7.
    P. Barroso, S. Iman, J. Jeong, K. Öner, M. Dubois, and K. Ramamurthy. RPM: a rapid prototyping engine for multiprocessor systems. IEEE Computer, (28):26–34, February 1995.Google Scholar
  8. 8.
    D. Lewis, D. Galloway, M. van Ierssel, J. Rose, and P. Chow. The Transmogrifier-2: A 1 million gate rapid prototyping system. In In Proceedings of ACM Symposium on FPGAs, pages 53–61, Monterey, CA, February 1997. ACM.Google Scholar
  9. 9.
    Altera Corporation. University Program Design Laboratory Package User Guide, August 1997. Version 1.Google Scholar
  10. 10.
    S. Sawitzki, A. Gratz, and R. Spallek. CoMPARE: A simple reconfigurable processor architecture exploiting instruction level parallelism. In K.A. Hawick and J.A. Heath, editors, Proceedings of the 5th Australasian Conference on Parallel and Real-Time Systems (PART’98), pages 213–224, Berlin Heidelberg New York, 1998. Springer-Verlag.Google Scholar
  11. 11.
    Hyperstone Electronics GmbH. Hyperstone E1-32/E1-16. 32-Bit-Microprocessor User’s Manual, 1997. Revision 03/97.Google Scholar
  12. 12.
    J. Eldredge and B. Hutchings. Density enhancement of a neural network using FP-GAs and run-time reconfiguration. In K. Pocek and J. Arnold, editors, Proceedings of FCCM’94, pages 180–188, Napa, CA, April 1994. IEEE.Google Scholar
  13. 13.
    Atmel Corporation. AT94K Series Field Programmable System Level Integrated Circuit Advance Information, 1999. Revision 1138B-12/99.Google Scholar
  14. 14.
    C. Wilson. The SUIF Guide. Stanford University, 1998.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Sergej Sawitzki
    • 1
    • 2
  • Steffen Köhler
    • 1
  • Rainer G. Spallek
    • 1
  1. 1.Institute of Computer EngineeringDresden University of TechnologyDresdenGermany
  2. 2.Philips Research LaboratoriesAA EindhovenThe Netherlands

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