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Chip-Based Reconfigurable Task Management

  • Gordon Brebner
  • Oliver Diessel
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

Modularity is a key aspect of system design, particularly in the era of system-on-chip. Field-programmable logic (FPL), particularly with the rapid increase in programmable gate counts, is a natural medium to host run-time modularity, that is, a dynamically-varying ensemble of circuit modules. Prior research has presumed the use of an external processor to manage such an ensemble. In this paper, we consider on-chip management, implemented in the FPL itself, based upon a one-dimensional allocation model. We demonstrate an algorithm for on-chip identification of free FPL resource for modules, and an approach to on-chip rearrangement of modules. The latter includes a proposal for a realistic augmentation to existing FPGA reconfiguration architectures. The work represents a key demonstration of how FPL can be used as a first-order computational resource, rather than just as a slave to the microprocessor.

Keywords

Realistic Augmentation Task Management Logic Resource Annual IEEE Symposium Free Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Gordon Brebner
    • 1
  • Oliver Diessel
    • 2
  1. 1.Division of InformaticsUniversity of EdinburghEdinburghUK
  2. 2.School of Computer Science & EngineeringUniversity of New South WalesSydneyAustralia

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