Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm
A single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm, Rijndael is presented. Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGA device. This proves to be one of the fastest single-chip FPGA Rijndael implementations currently available. The high Block RAM content of the Virtex-E device is exploited in the design.
KeywordsFPGA Implementation AES Rijndael Encryption
Unable to display preview. Download preview PDF.
- 1.J. Daemen, V. Rijmen; The Rijndael Block Cipher: AES Proposal; First AES Candidate Conference (AES1); August 20–22, 1998Google Scholar
- 2.NIST; Advanced Encryption Standard (AES) FIPS Draft Publication; URL: http://csrcnistgov/encryption/aes/: 28 February, 2001
- 3.Xilinx Virtex™-E Extended Memory 1.8V Field Programmable Gate Arrays; URL: http://www.xilinx.com: November 2000.
- 4.P. Chodowiec, P. Khuon, K. Gaj; Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner-and Outer-Pipelining; FPGA 2001, 11-13 February 2001, California.Google Scholar
- 5.A. Dandalis, V.K. Prasanna, J.D.P. Rolim; A Comparative Study of Performance of AES Candidates Using FPGAs; The Third Advanced Encryption Standard (AES3) Candidate Conference, 13-14 April 2000, New York, USA.Google Scholar
- 6.AJ. Elbirt, W. Yip, B. Chetwynd, C. Paar; An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists; AES3 Conference, 13-14 April 2000, New York, USA.Google Scholar
- 7.Brian Gladman: The AES Algorithm (Rijndael) in C and C++: URL: http://fp.gladman.plus.com/cryptographj_technology/rijndael/index.htm: April 2001.
- 8.M. McLoone, J. V. McCanny; High Peformance Single-Chip FPGA Rijndael Algorithm Implementations; Cryptographic Hardware and Embedded Systems-CHES 2001Google Scholar
- 9.K. NechBarker, Bassham, Burr, Dworkin, Foti, Roback; Report on the Development of the Advanced Encryption Standard (AES); URL: http://csrc.nist.gov/encryption/aes/: 2 October, 2000.
- 10.M. McLoone, J.V. McCanny: Apparatus for Selectably Encrypting and Decrypting Data: UK Patent Application No. 0107592.8: Filed March 2001.Google Scholar