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PuMA++: From Behavioral Specification to Multi-FPGA-Prototype

  • Klaus Harbich
  • Erich Barke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

In this paper we present a new design flow for efficient hardware implementation of behavioral system specifications at algorithmic level into heterogeneous multi-FPGA (Field-Programmable Gate Arrays) rapid prototyping systems. We discuss the benefits of coupling the high-level synthesis tool CADDY-II and the partitioning and mapping environment PUMA, which is designed for optimized implementation of RT-level (Register-Transfer) netlists into multi-FPGA architectures. With our new approach, rapid prototyping and in-circuit verification in earliest design phases are enabled. Due to short implementation times and precise back annotation accomplished by a close coupling of the tools, more design iterations and thus better design space exploration is possible.

Keywords

Rapid Prototype Clock Cycle Design Space Exploration Algorithmic Level Behavioral Specification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Klaus Harbich
    • 1
  • Erich Barke
    • 1
  1. 1.Institute of Microelectronic Circuits and Systems Design Automation GroupUniversity of HannoverHannoverGermany

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