Synthesizing RTL Hardware from Java Byte Codes
A structural design tool called JHDL was developed to aid in the design of high-performance pre-placed circuit macros for FPGAs . This tool was successfully used to design and field several high-performance reconfigurable computing systems. Examples of systems developed with this tool include a multi-FPGA sonar beamforming system and an automatic target recognition system. In these examples, the reconfigurable systems developed with JHDL achieve at least an order of magnitude performance improvement over programmable processors by exploiting parameterized module generators.
KeywordsBasic Block Synthesis Tool Behavioral Description Data Flow Graph Java Compiler
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