Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing

  • Abbes Amira
  • Ahmed Bouridane
  • Peter Milligan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


This paper investigates how some of the new features of the Xilinx Virtex FPGA may be used to support efficient and optimised implementation of matrix product based on Multiply and Accumulate (MAC) such operations are frequently used in signal applications. The principle new features that have been investigated are the Block RAM and the fully digital Delay-Locked Loop (DLL). The approach used for the matrix multiplication algorithm employs the idea used in the modified Booth encoder multiplication using Wallace Trees addition. Preliminary performance results and comparisons with similar algorithms implemented on multi-FPGA platforms have shown better performance for the proposed architecture.


Full Adder Reconfigurable Hardware FPGA Chip Matrix Multiplication Algorithm Matrix Multiplier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Abbes Amira
    • 1
  • Ahmed Bouridane
    • 1
  • Peter Milligan
    • 1
  1. 1.School of Computer ScienceThe Queen’s University of BelfastBelfastNorthern Ireland

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