Advertisement

Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing

  • Abbes Amira
  • Ahmed Bouridane
  • Peter Milligan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

This paper investigates how some of the new features of the Xilinx Virtex FPGA may be used to support efficient and optimised implementation of matrix product based on Multiply and Accumulate (MAC) such operations are frequently used in signal applications. The principle new features that have been investigated are the Block RAM and the fully digital Delay-Locked Loop (DLL). The approach used for the matrix multiplication algorithm employs the idea used in the modified Booth encoder multiplication using Wallace Trees addition. Preliminary performance results and comparisons with similar algorithms implemented on multi-FPGA platforms have shown better performance for the proposed architecture.

Keywords

Full Adder Reconfigurable Hardware FPGA Chip Matrix Multiplication Algorithm Matrix Multiplier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    W.B. Ligon III, S. McMillan and al., “A re-evaluation of the practicality of floating-point operation on FPGAs.” IEEE Symposium on FPGAs for Custom Computing Machines, pp. 206–215, April 15–17, 1998.Google Scholar
  2. [2]
    J. Poldre, K. Tammemaee, “Reconfigurable Multiplier for Virtex FPGA Family.” Lecture notes in computer science, Vol. 1673, pp. 359–364, 1999.Google Scholar
  3. [3]
    D.A. Patterson, J.L. Hennessy, and D. Goldberg, “Computer Architecture, A Quantitative Approach.” Appendix A, second ed. Morgan Kaufmann, 1996.Google Scholar
  4. [4]
    P. Graham and B. Nelson “FPGA-Based Sonar Processing.” Proceedings of the sixth ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA 1998), February 22–25 2001, Monterey, CA, USA.Google Scholar
  5. [5]
    A. Amira, A. Bouridane, P. Milligan and P. Sage “A High Throughput FPGA Implementation of A Bit-Level Matrix Product.” Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS), pp 356–364, October 2000, Lafeyette, LA, USA.Google Scholar
  6. [6]
    C.S. Wallace “A Suggestion for Fast Multiplier.” IEEE Transaction On Electronic Computers, VOL. 13, pp14–17, February 1964.Google Scholar
  7. [7]
  8. [8]
    O. Mencer, M. Morf and M J. Flynn, “PAM-Blox: High Performance FPGA Design for Adaptive Computing.” IEEE Symposium on EPGAs for Custom Computing Machines (FCCM), 1998 Napa Valley.Google Scholar
  9. [9]
    A. Amira, A. Bouridane and P. Milligan “RCMAT: a Reconfigurable Coprocessor for Matrix Algorithms.” Proceedings of the Ninth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2001), Monterey, pp 228, February 11–13 2001, Monterey, CA, USA.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Abbes Amira
    • 1
  • Ahmed Bouridane
    • 1
  • Peter Milligan
    • 1
  1. 1.School of Computer ScienceThe Queen’s University of BelfastBelfastNorthern Ireland

Personalised recommendations