Advertisement

Implementation of (Normalised) RLS Lattice on Virtex

  • Felix Albu
  • Jiri Kadlec
  • Chris Softley
  • Rudolf Matousek
  • Antonin Hermanek
  • Nick Coleman
  • Anthony Fagan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32bit logarithmic arithmetic. On Virtex XCV2000E-6, it takes 22% and 27% of slices respectively and performs at 45 MHz. The cores outperform (4-5 times) the standard DSP solution based on 32 bit floating point TMS320C3x/4x 50MHz processors.

Keywords

Clock Cycle Posteriori Error Standard Prediction Error Persistent Excitation Logarithmic Number System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    J.N. Coleman, E.I. Chester, ‘A 32-bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point’, 14th Symposium on Computer Arithmetic’, Adelaide, April 1999Google Scholar
  2. [2]
    Paulo S.R. Diniz, Algorithms and Practical Implementation, Kluwer Academic Publishers, 1997Google Scholar
  3. [3]
    J.N. Coleman, E. Chester, C. Softley and J. Kadlec “Arithmetic on the European Logarithmic Microprocessor”, IEEE Trans. Comput. Special Edition on Computer Arithmetic, July 2000. Vol. 49, No. 7, p702–715.Google Scholar
  4. [4]
    Coleman J. N., Kadlec J.: Extended Precision Logarithmic Arithmetics. In Proceedings of the 34-th IEEE Asilomar Conference on Signals, Systems and Computers, Monterey USA. November 2000.Google Scholar
  5. [5]
    J. Kadlec, A. Hermanek, Ch. Softley, R. Matousek, M. Licko “32-bit Logarithmic ALU for Handel C 2.1 and Celoxica DK1 (53 MHz for XCV2000E-6 based RC1000 board)” Results will be presented at Celoxica user conference (In Stratford, UK, 2–3. April, 2001. Download from: http://www.celoxica.com/programs/universitv/academic_papers.ntm
  6. [6]
    RC1000-PP Hardware Reference Manual, Celoxica, United Kingdom http://www.celoxica.eom/products/boards/DATRHD001.2.pdf
  7. [7]
    R.L. Walke, R.W.M. Smith, G. Lightbody, “20 GFLOPS QR processor on a Xilinx Virtex-E FPGA”, SPIE, San Diego, 2000, U.S.AGoogle Scholar
  8. [8]
    RL. Walke, J. Dudley, “An FPGA based digital radar receiver for Soft Radar”, 34th Asilomar Conference on Signals, Systems, and Computers, Monterey, 2000, California, U.S.AGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Felix Albu
    • 1
  • Jiri Kadlec
    • 2
  • Chris Softley
    • 3
  • Rudolf Matousek
    • 2
  • Antonin Hermanek
    • 2
  • Nick Coleman
    • 3
  • Anthony Fagan
    • 1
  1. 1.University College DublinIreland
  2. 2.UTIA PragueCzech Republic
  3. 3.University of Newcastle upon TyneUK

Personalised recommendations