Abstract
An FPGA based Artificial Neural Network is proposed. The neuron is based on a spiking scheme where signals are encoded in a stochastic pulse train. The neuron is composed of a synaptic module and a summing-activation module. The architecture of the neuron is characterized and its FPGA implementation is presented. The basic spiking neuron is used to implement a basic neural network. An extension of the neuron architecture to include an address-event protocol for signal multiplexing in a single line is proposed. VHDL simulations and FPGA synthesis results are discussed.
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© 2000 Springer-Verlag Berlin Heidelberg
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Maya, S., Reynoso, R., Torres, C., Arias-Estrada, M. (2000). Compact Spiking Neural Network Implementation in FPGA. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_30
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DOI: https://doi.org/10.1007/3-540-44614-1_30
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