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Compiler-Directed Dynamic Frequency and Voltage Scheduling

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Power-Aware Computer Systems (PACS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2008))

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Abstract

Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies opportunities for dynamic voltage and frequency scaling of the CPU without significant increase in overall program execution time. The paper introduces a simple, yet effective performance model to determine an effcient CPU slow-down factor for memory bound loop computations. Simulation results of a superscalar target architecture and a program kernel compiled at different optimizations levels show the potential benefit of the proposed compiler optimization. The energy savings are reported for a hypothetical target machine with power dissipation characteristics similar to Transmeta's Crusoe TM5400 processor.

This research was partially supported by NSF CAREER award CCR-9985050 and a Rutgers University ISC Pilot Project grant.

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References

  1. R. Bahar, G. Albera, and S. Manne. Power and performance tradeoffs using various caching strategies. In International Symposium on Low Power Electronic Design (ISLPED), pages 70–75, August 1998.

    Google Scholar 

  2. F. Bassetti. A lower bound for qualtifying overlap effects: An empirical approach. In Submitted to International Performance, Computing, and Communications Conference, 1998.

    Google Scholar 

  3. L. Benini and G. Micheli. System-level power optimization: Techniques and tools. ACM Transactions on Design Automation of Electronic Systems, 5:115–192, April 2000.

    Google Scholar 

  4. C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto. An instruction-level functionality-based energy estimation model for 32-bits microprocessors. In 37th IEEE-Design Automation Conference (DAC), pages 346–351, June 2000.

    Google Scholar 

  5. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architecturallevel power analysis and optimizations. In 27th International Symposium on Computer Architecture (ISCA), June 2000.

    Google Scholar 

  6. T. Burd and R. Brodersen. Processor design for portable systems. Journal of VLSI Signal Processing, 13(2–3):203–222, 1996.

    Google Scholar 

  7. T. Burd and R. Brodersen. Design issues for dynamic voltage scaling. In International Symposium on Low Power Electronics and Design (ISLPED), July 2000.

    Google Scholar 

  8. T. Burd, T. Pering, A. Stratakos, and R. Brodersen. A dynamic voltage-scaled microprocessor system. In IEEE International Solid-State Circuits Conference (ISSCC-2000), February 2000.

    Google Scholar 

  9. D. Burger and T. Austin. The SimpleScalar tool set version 2.0. Technical Report 1342, Computer Science Department, University of Wisconsin, June 1997.

    Google Scholar 

  10. D. Burger, A. Kägi, and M. Hrishikesh. Memory hierarchy extensions to SimpleScalar 3.0. Technical Report TR99-25, Department of Computer Science, University of Texas at Austin, April 1999.

    Google Scholar 

  11. D. Callahan, J. Cocke, and K. Kennedy. Estimating interlock and improving balance for pipelined architectures. Journal of Parallel and Distributed Computing, 5(4):334–358, August 1988.

    Google Scholar 

  12. S. Carr and K. Kennedy. Improving the ratio of memory operations to floatingpoint operations in loops. ACM Transactions on Programming Languages and Systems, November 1994.

    Google Scholar 

  13. J. Chang and M. Pedram. Energy minimization using multiple supply voltages. In International Symposium on Low Power Electronics and Design (ISLPED-96), pages 157–162, August 1996. also published in IEEE Transaction on VLSI Systems 5(4): Dec 1997.

    Google Scholar 

  14. K. Govil, E. Chan, and H. Wasserman. Comparing algorithms for dynamic speedsetting of a low-power CPU. In the 1st ACM International Conference on Mobile Computing and Networking (MOBICOM-95), pages 13–25, November 1995.

    Google Scholar 

  15. P. Hicks, M. Walnock, and R. Owens. Analysis of power consumption in memory hierarchies. In International Symposium on Low Power Electronics and Design (ISLPED-97), pages 239–242, 1997.

    Google Scholar 

  16. T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In International Symposium on Low Power Electronics and Design (ISLPED-98), pages 197–202, August 1998.

    Google Scholar 

  17. L. John, V. Reddy, P. Hulina, and L. Coraor. Program balance and its impact on high performance RISC architectures. In Proceedings of the First International Symposium on High-Performance Computer Architecture, pages 370–379, January 1995.

    Google Scholar 

  18. M. Kamble and K. Ghose. Analytical energy dissipation models for low power caches. In Proceedings of 1997 International Symposium on Low Power Electronics and Design (ISLPED), pages 143–148, 1997.

    Google Scholar 

  19. M. Kandemir, N. Vijaykrishnan, M.J. Irwin, and H.S. Kim. Experimental evaluation of energy behavior of iteration spacetiling. In International Workshop on Languages and Compilers for Parallel Computing (LCPC), August 2000.

    Google Scholar 

  20. M. Kandemir, N. Vijaykrishnan, M.J. Irwin, and W. Ye. Influence of compiler optimizations on system power. In Design Automation Conference (DAC), June 2000.

    Google Scholar 

  21. K. Kennedy and U. Kremer. Automatic data layout for distributed memory machines. ACM Transactions on Programming Languages and Systems, 20(4):869–916, July 1998.

    Article  Google Scholar 

  22. U. Kremer, J. Hicks, and J. Rehg. Compiler-directed remote task execution for power management. In Workshop on Compilers and Operating Systems for Low Power (COLP’00), October 2000.

    Google Scholar 

  23. D. Kroft. Lockup-free instruction fetch/prefetch cache organization. In Proceedings of the 18th International Symposium on Computer Architecture (ISCA-81), pages 81–87, May 1981.

    Google Scholar 

  24. T. Martin and D. Siewiorek. The impact of battery capacity and memory bandwidth on cpu speed-setting: a case study. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED’99), August 1999.

    Google Scholar 

  25. J. McCalpin. Memory bandwidth and machine balance in current high performance computers. IEEE Technical Committee on Computer Architecture Newsletter, December 1995.

    Google Scholar 

  26. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, Inc., 1997.

    Google Scholar 

  27. T. Pering and R. Brodersen. Energy efficient voltage scheduling for real-time operating systems. In 4th IEEE Real-Time Technology and Applications Symposium (RTAS-98), Working in Progress Section, 1998.

    Google Scholar 

  28. T. Pering, T. Burd, and R. Brodersen. The simulation and evaluation of dynamic voltage scaling algorithms. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED-98), pages 76–81, New York, August 1998. ACM Press.

    Google Scholar 

  29. G. Qu, N. Kawabe, K. Usami, and M. Potkonjak. Function-level power estimation methodology for microprocessors. In Design Automation Conference (DAC), June 2000.

    Google Scholar 

  30. G. Sohi. Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Transactions on Computers, 39(3):349–359, March 1990.

    Article  Google Scholar 

  31. C. Su and A. Despain. Cache design trade-offs for power and performance optimization: A case study. In International Symposium on Low Power Electronics and Design (ISLPED), pages 63–68, 1995.

    Google Scholar 

  32. V. Tiwari, S. Malik, A. Wolfe, and M. Lee. Instruction level power analysis and optimization of software. Journal of VLSI Signal Processing, 13(2/3):1–18, 1996.

    Google Scholar 

  33. M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. In the 1st Symposium on Operating Systems Design and Implementation (OSDI-94), pages 13–23, November 1994.

    Google Scholar 

  34. M. Wolfe. High Performance Compilers for Parallel Computing. Addison-Wesley Co., 1996.

    Google Scholar 

  35. W. Ye, N. Vijaykrishna, M. Kandemir, and M.J. Irwin. The design and use of SimplePower: A cycle-accurate energy estimation tool. In Design Automation Conference (DAC), June 2000.

    Google Scholar 

  36. Y. Zhang, R. Chen, and M.J. Irwin. System level interconnect modeling. In Proceedings of the 11th IEEE International ASIC Conference, September 1998.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Computer Science, Rutgers University, Piscataway, New Jersey, USA

    Chung-Hsing Hsu & Ulrich Kremer

  2. Department of Electrical and Computer Engineering, Rutgers University, Piscataway, New Jersey, USA

    Michael Hsiao

Authors
  1. Chung-Hsing Hsu
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  2. Ulrich Kremer
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  3. Michael Hsiao
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Editor information

Editors and Affiliations

  1. Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., PA 15213, Pittsburgh, USA

    Babak Falsafi

  2. School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, IN 47907, W.Lafayette, USA

    T. N. Vijaykumar

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© 2001 Springer-Verlag Berlin Heidelberg

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Hsu, CH., Kremer, U., Hsiao, M. (2001). Compiler-Directed Dynamic Frequency and Voltage Scheduling. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2000. Lecture Notes in Computer Science, vol 2008. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44572-2_6

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  • DOI: https://doi.org/10.1007/3-540-44572-2_6

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42329-4

  • Online ISBN: 978-3-540-44572-2

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