Abstract
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of the VIRAM architecture from the perspective of compiler writers, describing some of the code generation problems that arise in VIRAM and their solutions in the VIRAM compiler. VIRAM is a single chip system designed primarily for multimedia. It combines vector processing with mixed logic and DRAM to achieve high performance with relatively low energy, area, and design complexity. The paper focuses on two aspects of the VIRAM compiler and architecture. The first problem is to take advantage of the on-chip bandwidth for memory-intensive applications, including those with non-contiguous or unpredictable memory access patterns. The second problem is to support that kinds of narrow data types that arise in media processing, including processing of 8 and 16-bit data.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
E. Anderson, Z. Bai, C. Bischof, S. Blackford, J. Demmel, J. Dongarra, J. Du Croz, A. Greenbaum, S. Hammarling, A. McKenney, and D. Sorenson. LAPACK Users’ Guide: Third Edition. SIAM, 1999.
R. Fromm, S. Perissakis, N. Cardwell, C. Kozyrakis, B. McGaughy, D. Patterson, T. Anderson, and K. Yelick. The energy efficiency of IRAM architectures. In the 24th Annual International Symposium on Computer Architecture, pages 327–337, Denver, CO, June 1997.
C.E. Kozyrakis, J. Gebis, D. Martin, S. Williams, I. Mavroidis, S. Pope, D. Jones, D. Patterson, and D. Yelick. VIRAM: A Media-oriented Vector Processor with Embedded DRAM. In the Conference Record of the 12th Hot Chips Symposium, Palo Alto, CA, August 2000.
Christoforos Kozyrakis. A media-enhanced vector architecture for embedded memory systems. Technical Report UCB//CSD-99-1059, University of California, Berkeley, July 1999.
C.G. Lee and M.G. Stoodley. Simple vector microprocessors for multimedia applications. In 31st Annual International Symposium on Microarchitecture, December 1998.
D. Martin. Vector Extensions to the MIPS-IV Instruction Set Architecture. Computer Science Division, University of California at Berkeley, January 1999.
D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick. A case for Intelligent DRAM: IRAM. IEEE Micro, 17(2):34–44, April 1997.
M. Phillip. A second generation SIMD microprocessor architecture. In Proceedings of the Hot Chips X Symposium, August 1998.
A. Peleg and U. Weiser. MMX technology extension to the intel architecture. IEEE Micro, 16(4):42–50, August 1996.
M. Stephenson, J. Babb, and S. Amarasinghe. Bitwidth analysis with application to silicon compilation. In Proceedings of the SIGPLAN conference on Programming Language Design and Implementation, Vancouver, British Columbia, June 2000.
Randi Thomas. An architectural performance study of the fast fourier transform on VIRAM. Technical Report UCB//CSD-99-1106, University of California, Berkeley, June 2000.
T. Yamauchi et al. The hierarchical multi-bank DRAM: a high-performance architecture for memory integrated with processors. In the Proceedings of the 17th Conf. on Advanced Research in VLSI, Ann Arbor, MI, Sep 1997.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Judd, D., Yelick, K., Kozyrakis, C., Martin, D., Patterson, D. (2001). Exploiting On-chip Memory Bandwidth in the VIRAM Compiler. In: Chong, F.T., Kozyrakis, C., Oskin, M. (eds) Intelligent Memory Systems. IMS 2000. Lecture Notes in Computer Science, vol 2107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44570-6_8
Download citation
DOI: https://doi.org/10.1007/3-540-44570-6_8
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42328-7
Online ISBN: 978-3-540-44570-8
eBook Packages: Springer Book Archive