Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems

Abstract

The idea of Force-Directed Scheduling (FDS) was first introduced by Paulin and Knight [1] to minimize the number of resources required in the high-level synthesis of high-throughput ASICs. In the frame of our recent Data Transfer and Storage Exploration (DTSE) research [7],[15],[18], we have extended FDS for low-cost¹ scheduling in real-time embedded system synthesis. We have shown that FDS is in fact a projected solution to a more general multi-dimensional space/time scheduling problem [19]. By using this reformulation and by introducing (very) low-complexity dynamic and clustering graph techniques [21], we have shown that the interactive design of low-cost but still high-throughput telecom networks, speech, image and video embedded systems is feasible using a runtime parameterizable Generalized Conflict-Directed Ordering (G-CDO(k)) algorithm. Because G-CDO(k) is based on a true multi-dimensional design space exploration mechanism, it is in principle able to analyze design bottlenecks with a much higher resolution than any other technique. In this paper, we develop novel multi-dimensional selection techniques to allow this powerful feature. Experiments of redesigning the large-scale and parallel Segment Protocol Processor (SPP) from Alcatel give promising results.

By low-cost embedded system, we refer to an embedded system exhibiting a good compromise between low-power, low-bandwidth, low-memory size (i.e. low-area) and also low-runtime (i.e. fast). In our DTSE methodology, this compromise is parameterizable and is a pragmatic choice left to the designer.