Abstract
Architects of future generation processors will have hundreds of millions of transistors with which to build computing chips. At the same time, it is becoming clear that naive scaling of conventional (superscalar) designs will increase complexity and cost while not meeting performance goals. Consequently, many computer architects are advocating a shift in focus from high-performance to high-throughput with a corresponding shift to multithreaded architectures. Multithreaded architectures provide new opportunities for extracting parallelism from a single program via thread level speculation. We expect to see two major forms of thread-level speculation: control-driven and data-driven. We believe that future processors will not only be multithreaded, but will also support thread-level speculation, giving them the flexibility to operate in either multiple-program/high-throughput or single-program/highperformance capacities. Deployment of such processors will require innovations in means to convey multithreading information from software to hardware, algorithms for thread selection and management, as well as hardware structures to support the simultaneous execution of collections of speculative and non-speculative threads.
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References
H. Akkary and M.A. Driscoll. A Dynamic Multithreading Processor. In Proc. 31st International Symposium on Microarchitecture, pages 226–236, Nov. 1998.
Arvind and R.S. Nikhil. Executing a Program on the MIT Tagged-Token Dataflow Architecture. IEEE Transactions on Computers, 39(3):300–318, Mar. 1990.
R.S. Chappell, J. Stark, S.P. Kim, S.K. Reinhardt, and Y.N. Patt. Simultaneous Subordinate Microthreading (SSMT). In Proc. 26th International Symposium on Computer Architecture, May 1999.
G.Z. Chrysos and J.S. Emer. Memory Dependence Prediction using Store Sets. In Proc. 25th International Symposium on Computer Architecture, pages 142–153, Jun. 1998.
G.E. Daddis and H.C. Torng. The concurrent execution of multiple instruction streams on superscalar processors. In Proc. International Conference on Parallel Processing, pages 76–83, May 1991.
P.K. Dubey, K. O’brien, K.A. O’brien, and C. Barton. Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading. In Proc. 1995Conference on Parallel Architectures and Compilation Techniques, pages 109–121, Jun. 1995.
J. Emer. Simultaneous Multithreading: Multiplying Alpha’s Performance. Microprocessor Forum, Oct. 1999.
A. Farcy, O. Temam, R. Espasa, and T. Juan. Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. In Proc. 31st International Symposium on Microarchitecture, pages 59–68, Dec. 1998.
M. Franklin. The Multiscalar Architecture. PhD thesis, University of Wisconsin-Madison, Madison, WI 53706, Nov. 1993.
M. Franklin and G.S. Sohi. ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Transactions on Computers, May 1996.
S. Gopal, T.N. Vijaykumar, J.E. Smith, and G.S. Sohi. Speculative Versioning Cache. In Proc. 4th International Symposium on High-Performance Computer Architecture, pages 195–205, Feb. 1998.
L. Hammond, B.A. Nayfeh, and K. Olukotun. A Single-Chip Multiprocessor. IEEE Computer, 30(9):79–85, Sep. 1997.
L. Hammond, M. Willey, and K. Olukotun. Data speculation support for a chip multiprocessor. In Proc. 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 58–69, Oct. 1998.
H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa. An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. In Proc. 19th Annual International Symposium on Computer Architecture, pages 136–145, May 1992.
R.A. Iannucci. Toward a Dataflow/von Neumann Hybrid Architecture. In Proc. 15International Symposium on Computer Architecture, pages 131–140, May 1988.
Z. Li, J.-Y. Tsai, X. Wang, P.-C. Yew, and B. Zheng. Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support. In Proc. 9th Workshop on Languages and Compilers for Parallel Computing, Aug. 1996.
A. Moshovos, S.E. Breach, T.N. Vijaykumar, and G.S. Sohi. Dynamic Speculation and Synchronization of Data Dependences. In Proc. 24th International Symposium on Computer Architecture, pages 181–193, Jun. 1997.
N. Nishi, T. Inoue, M. Nomura, S. Matsushita, S. Toru, A. Shibayama, J. Sakai, T. Oshawa, Y. Nakamura, S. Shimada, Y. Ito, M. Edahiro, M. Mizuno, K. Minami, O. Matsuo, H. Inoue, T. Manabe, T. Yamazaki, Y. Nakazawa, Y. Hirota, and Y. Yamada. A 1 GIPS 1 W Single-Chip Tightly-Coupled Four-Way Multiprocessor with Architecture Support for Multiple Control-Flow Execution. In Proc. 47th International IEEE Solid-State Circuits Conference, Feb. 2000.
G. Papadopoulos and D. Culler. Monsoon: An Explict Token-Store Architecture. In Proc. 17th International Symposium on Computer Architecture, pages 82–91, Jul. 1990.
A. Roth, A. Moshovos, and G.S. Sohi. Dependence Based Prefetching for Linked Data Structures. In Proc. 8th Conference on Architectural Support for Programming Languages and Operating Systems, pages 115–126, Oct. 1998.
A. Roth, A. Moshovos, and G.S. Sohi. Improving Virtual Function Call Target Prediction via Dependence-Based Pre-Computation. In Proc. 1999 Internation Conference on Supercomputing, pages 356–364, Jun. 1999.
A. Roth and G.S. Sohi. Register Integration: A Simple and Efficent Implementation of Squash Re-Use. In Proc. 33rd Annual International Symposium on Microarchitecture, Dec. 2000.
A. Roth and G.S. Sohi. Speculative Data-Driven Multithreading. Technical Report CS-TR-00-1414, University of Wisconsin, Madison, Mar. 2000.
A. Roth, C.B. Zilles, and G.S. Sohi. Speculative Miss/Execute Decoupling. In Proc. Workshop on Memory Access Decoupling in Superscalar and Multithreaded Architectures, Oct. 2000.
S. Sakai, Y. Yamaguchi, K. Hiraki, Y. Kodama, and T. Yuba. An Architecture of a Dataflow Single Chip Processor. In Proc. 16th Annual International Symposium on Computer Architecture, pages 46–53, May 1989.
M. Sato, Y. Kodama, S. Sakai, Y. Yamaguchi, and Y. Koumura. Thread-based Programming for the EM-4 Hybrid Dataflow Machine. In Proc. 19th Annual International Symposium on Computer Architecture, pages 146–155, May 1992.
G.S. Sohi, S. Breach, and T.N. Vijaykumar. Multiscalar Processors. In Proc. 22nd International Symposium on Computer Architecture, pages 414–425, Jun. 1995.
Y.H. Song and M. Dubois. Assisted Execution. Technical Report #CENG 98-25, Department of EE-Systems, University of Southern California, Oct. 1998.
J.G. Steffan and T.C. Mowry. The Potential for Using Thread Level Data-Speculation to Facilitate Automatic Parallelization. In Proc. 4th International Symposium on High Performance Computer Architecture, Feb. 1998.
M. Takesue. A Uniffied Resource Management and Execution Control Mechanism for Data Flow Machines. In Proc. 14th Annual International Symposium on Computer Architecture, pages 90–97, Jun. 1987.
M. Tremblay. MAJC: An Architecture for the New Millenium. In Proc. Hot Chips 11, pages 275–288, Aug. 1999. http://www.sun.com/microelectronics/MAJC/documentation/docs/HC99sm.pdf.
D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. In Proc. 23rd International Symposium on Computer Architecture, pages 191–202, May 1996.
W. Yamamoto and M. Nemirovsky. Increasing Superscalar Performance Through Multistreaming. In Proc. 1995Confer ence on Parallel Architectures and Compilation Techniques, Jun. 1995.
Y. Zhang, L. Rauchwerger, and J. Torrellas. Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. In Proc. 4th International Symposium on High-Performance Computer Architecture, Feb. 1998.
C.B. Zilles and G.S. Sohi. Understanding the Backward Slices of Performance Degrading Instructions. In Proc. 27th International Symposium on Computer Architecture, pages 172–181, Jun. 2000.
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Sohi, G.S., Roth, A. (2000). Speculative Multithreaded Processors. In: Valero, M., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2000. HiPC 2000. Lecture Notes in Computer Science, vol 1970. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44467-X_23
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DOI: https://doi.org/10.1007/3-540-44467-X_23
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