Abstract
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the availability of billions of transistors. Many important applications will be object-oriented, multithreaded, and will consist of many separately compiled and dynamically linked parts. To accommodate these shifts in both technology and applications, microarchitectures will process instruction streams in a distributed fashion - instruction level distributed processing (ILDP). ILDP will be implemented in a variety of ways, including both homogeneous and heterogeneous elements. To help find run-time parallelism, orchestrate distributed hardware resources, implement power conservation strategies, and to provide fault-tolerant features, an additional layer of abstraction - the virtual machine layer - will likely become an essential ingredient. Finally, newinstruction sets may be necessary to better focus on instruction level communication and dependence, rather than computation and independence as is commonly done today.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Neil C. Wilhelm,“WhyWire DelaysWill No Longer Scaler for VLSI Chips,” SUN Microsystems Laboratories Technical Report TR-95-44, August 1995.
V. Agarwal, M. S. Hrishikesh, S.W. Keckler, D. Burger, “Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures,” 27th Int. Symp. on Computer Architecture, pp. 248–259, June 2000.
S. Thompson, P. Packan, and M. Bohr, “MOS Scaling: Transistor Challenges for the 21st Century,” Intel Technology Journal, Q3, 1998.
M. S. Pittler, D. Powers, D. L. Schnabel,“System Development and Technology Aspects of the IBM 3081 Processor Complex,” IBM J ournal of Research and Development,, pp. 2–11, Jan. 1982.
M. August, G. Brost, C. Hsiung, A. Schiffler, “Cray X-MP: The Birth of a Supercomputer,” IEEE Computer, pp. 45–52, January 1989.
R. Eichemeyer, et al. “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”, 23rd Annual Int. Symp. on Computer Architecture, pp. 203–212, June 1996.
K. Diefendorff,“Compaq Chooses SMT for Alpha,” Microprocessor Report, pp. 1, 6–11, Dec. 6, 1999.
L. Barroso, et al.,“Prianha: A Scalable Architecture Based on Single-Chip Multiprocessing,” 27th Int. Symp. on Computer Architecture,, pp. 282–293, June 2000.
W. Yamamoto, M. Nemirovsky,“Increasing Superscalar Performance Through Multistreaming,” 3rd Int. Symp. on Parallel Arch. and Compiler Techniques, June 1995.
D. Tullsen, S. Eggers and H. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism”, 22nd Annual International Symposium on Computer Architecture, June 1995.
B. Case,“Intel Reveals Pentium Implementation Details,”, Microprocessor Report, pp. 9–17, March 29, 1993.
Linley Gwennap,“Intel’s P6 Uses Decoupled Superscalar Design”, Microprocessor Report, pp. 9–15, Feb. 16, 1995.
G. Hinton,“Willamette: Next Generation IA-32 Micro-architecture,” Intel Developer Forum Spring 2000, Feb. 15, 2000. Intel Willamette
S. Palacharla, N. Jouppi, J. E. Smith, “Complexity-Effective Superscalar Processors,” 24th Int. Symp. on Computer Architecture,, pp. 206–218, June 1997.
L. Gwennap,“Digital 21264 Sets New Standard,” Microprocessor Report, pp. 11–16, Oct. 1996.
A. Roth and G. Sohi,“Effective Jump-Pointer Prefetching for Linked Data Structures,” 26th Int. Symp. on Computer Architecture,, pp. 111–121, May 1999.
8. G. Reinman, T. Austin, B. Calder,“A Scalable Front-End Architecture for Fast Instruction Delivery,” 26th Int. Symposium on Computer Architecture, pp. 234–245, May 1999.
Yuan Chou and J. P. Shen,“Instruction Path Coprocessors,” 27th Int. Symposium on Computer Architecture, pp. 270–281, June 2000.
Timothy Heil and J. E. Smith,“Concurrent Garbage Collection Using Hardware-Assisted Profiling,” International Symposium on Memory Management (ISMM), October 2000.
T. Austin,“DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,” 32nd Int. Symposium on Microarchitecture, pp. 196–297, Nov. 1999.
K. Ebcioglu and E. R. Altman,“DAISY: Dynamic Compilation for 100Compatibility,” 24th Int. Symp. on Computer Architecture,, June 1997.
A. Klaiber,“The Technology Behind Crusoe Processors,” Transmeta Technical Brief, 2000.
J. E. Smith, T. Heil, S. Sastry, T. Bezenek,“Achieving High Performance via Co-Designed Virtual Machines,” Intl. Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems,, pp. 77–84, Oct. 1998.
D. H. Albonesi,“The Inherent Energy Efficiency of Complexity-Adaptive Processors,” 1998 Power-Driven Microarchitecture Workshop, pp. 107–112, June 1998.
W. A. Wulf,“Compilers and Computer Architecture,” IEEE Computer, pp. 41–48, July 1981.
L. Gwennap,“Intel, HP Make EPIC Disclosure,” Microprocessor Report, pp. 1–9, Oct. 1997.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Smith, J.E. (2000). Instruction Level Distributed Processing. In: Valero, M., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2000. HiPC 2000. Lecture Notes in Computer Science, vol 1970. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44467-X_22
Download citation
DOI: https://doi.org/10.1007/3-540-44467-X_22
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41429-2
Online ISBN: 978-3-540-44467-1
eBook Packages: Springer Book Archive