Abstract
With the advent of system level integration (SLI) and system-on- chip (SOC), the center of gravity of the computer industry is moving from personal computing into embedded computing. The opportunities, needs and constraints of this next generation of computing are somewhat different from those to which we have got accustomed in general-purpose computing. This will lead to significantly different computer architectures, at both the system and the processor levels, and a rich diversity of off-the-shelf and custom designs. Furthermore, we predict that embedded computing will introduce a new theme into computer architecture: automation of architecture. In this paper, we elaborate on these claims and provide, as an example, an overview of PICO, the architecture synthesis system that the authors and their colleagues have been developing over the past five years.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Abraham, S., Rau, B.R. and Schreiber, R. Fast Design Space Exploration Through Validity and Quality Filtering of Subsystem Designs. Hewlett-Packard Laboratories Technical Report No. HPL-2000-98. Hewlett-Packard Laboratories, 2000.
Abraham, S.G. and Mahlke, S.A., Automatic and efficient evaluation of memory hierarchies for embedded systems. in Proc. 32nd Annual International Symposium on Microarchitecture (MICRO’ 99), (1999), IEEE Computer Society, 114–125.
Aditya, S., Rau, B.R. and Kathail, V., Automatic architectural synthesis of VLIW and EPIC processors. in Proc. International Symposium on System Synthesis, ISSS’99, (San Jose, California, 1999), IEEE Computer Society and the ACM, 107–113.
Elliot, J.P. Understanding Behavorial Synthesis: A Practical Guide to High-Level Design. Kluwer Academic, 1999.
Gonzalez, R.E. Xtensa: a configurable and extensible processor. IEEE Micro, 20 (2). 60–70, 2000.
Kathail, V., Schlansker, M. and Rau, B.R. HPL-PD Architecture Specification: Version 1.1. Hewlett-Packard Laboratories Technical Report No. HPL-93-80 (R.1). Hewlett-Packard Laboratories, 2000.
Knapp, D.W. Behavorial Synthesis: Digital System Design Using The Synopsys Behavorial Compiler. Prentice Hall PTR, Upper Saddle River, New Jersey, 1996.
Lee, W.F. VHDL: Coding and Logic Synthesis with Synopsys. Academic Press, 2000.
Rau, B.R., Kathail, V. and Aditya, S. Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems, 4 (2/3). 71–118, 1999.
Schlansker, M.S. and Rau, B.R. EPIC: Explicitly Parallel Instruction Computing. Computer, 33 (2). 37–45, 2000.
Schreiber, R., Aditya, S., Rau, B.R., Kathail, V., Mahlke, S., Abraham, S. and Snider, G., High-level synthesis of nonprogrammable hardware accelerators. in Proc. International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), (Boston, Massachussetts, 2000), IEEE Computer Society, 113–124.
Sharma, A.K. Programmable Logic Handbook: PLDs, CPLDs, and FPGAs. McGraw Hill Companies, 1998.
Sugumar, R.A. and Abraham, S.G., Efficient Simulation of Caches under Optimal Replacement with Applications to Miss Characterization. in Proc. ACM SIGMETRICS, (1993), 24–35.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rau, B.R., Schlansker, M.S. (2000). Embedded Computing: New Directions in Architecture and Automation. In: Valero, M., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2000. HiPC 2000. Lecture Notes in Computer Science, vol 1970. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44467-X_21
Download citation
DOI: https://doi.org/10.1007/3-540-44467-X_21
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41429-2
Online ISBN: 978-3-540-44467-1
eBook Packages: Springer Book Archive