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Power: A First Class Design Constraint for Future Architectures

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1970))

Abstract

In many mobile and embedded environments power is already the leading design constraint. This paper argues that power will also be a limiting factor in general purpose high-performance computers too. It should therefore be considered a “first class” design constraint on a par with performance. A corollary of this view is that the impact of architectural design decisions on power consumption must be considered early in the design cycle at the same time that their performance impact is considered. In this paper we summarize the key equations governing power and performance, and use them to illustrate some simple architectural ideas for power savings. The paper then presents two contrasting research directions where power is important. We conclude with a discussion of the tools needed to conduct research into architecture-power trade-offs.

Author’s address: Dept. EECS, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI 48109-2122, USA. WWW: http://www.eecs.umich.edu/~tnm.

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References

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© 2000 Springer-Verlag Berlin Heidelberg

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Mudge, T. (2000). Power: A First Class Design Constraint for Future Architectures. In: Valero, M., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2000. HiPC 2000. Lecture Notes in Computer Science, vol 1970. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44467-X_20

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  • DOI: https://doi.org/10.1007/3-540-44467-X_20

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41429-2

  • Online ISBN: 978-3-540-44467-1

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