Physical Design of CMOS Chips in Six Easy Steps

  • Sidney E. Benda
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1963)


Aimed at software professional not familiar with design processes of semiconductor elements that execute their programs. This paper focuses on algorithms and software involved in a design, layout and verification of CMOS parts. The first section introduces basic building elements of a design—transistor and standard cell—and shows their representation in design database. The design flow is segmented into six distinct steps: design capture, synthesis, floorplanning, placement and routing, extraction and verification.


Metal Layer Standard Cell Design Database Hardware Description Language Easy Step 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    E. Cheng. Risa: Accurate and efficient placement routability modeling. In ICCAD’ 94 Proceedings. IEEE Computer Society Press, 1994. 125Google Scholar
  2. 3.
    K. M. Hall. An r-dimensional quadratic placement algorithm. Management Science, 17, 1970. 122Google Scholar
  3. 4.
    P. Kurup and T. Abbasi. Logic Synthesis Using Synopsys. Kluwer Academic Publishers, 1997.Google Scholar
  4. 5.
    C. Y. Lee. An Algorithm for Path Connections and Its Applications. IEEE Transaction on Electronic Computers. 1961. 124Google Scholar
  5. 6.
    S. Malik and R. Rudell. Multi-level Logic Synthesis. ICCAD’92 Tutorial. IEEE Computer Society Press, 1992.Google Scholar
  6. 7.
    H. Murata, K. Fujioshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module placement. In ICCAD’ 95 Proceedings. IEEE Computer Society Press, 1995. 121Google Scholar
  7. 8.
    B. Preas and M. Lorenzetti. Physical Design Automation of VLSI Systems. The Benjamin/Cummings Publishing Co., Inc., 1988. 122, 127Google Scholar
  8. 9.
    G. Rabbat. Handbook of Advanced Semiconductor Technology and Computer Systems. Van Nostrand Reinhold Company Inc., 1988.Google Scholar
  9. 10.
    N. Sherwani. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, 1993. 122Google Scholar
  10. 11.
    W. Shi. An optimal algorithm for area minimization of slicing floorplans. In ICCAD’ 95 Proceedings. IEEE Computer Society Press, 1995. 121Google Scholar
  11. 12.
    J. Soukup. Fast maze router. In Proceedings of 15th Design Automation Conference, pages 100–102, 1978. 124Google Scholar
  12. 15.
    N. Weste and K. Esraghian. Principles of CMOS VLSI Design. Addison-Wesley Publishing Co., 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Sidney E. Benda
    • 1
  1. 1.Colorado Springs Design CenterIntel Corp.USA

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