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Speeding Up Image Computation by Using RTL Information

  • Christoph Meinel
  • Christian Stangier
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1954)

Abstract

Image computation is the core operation for optimization and formal verification of sequential systems like controllers or proto- cols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes man- ageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of controllers given in the hardware description language Verilog. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction both in CPU time and memory consumption.

Keywords

Model Check Transition Relation Memory Consumption Reachable State Reachability Analysis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Christoph Meinel
    • 1
  • Christian Stangier
    • 1
  1. 1.FB InformatikUniversity of TrierUSA

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