Skip to main content
SpringerLink
Log in

Limits of Task-based Parallelism in Irregular Applications

  • Conference paper
  • First Online:
High Performance Computing (ISHPC 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1940))

Included in the following conference series:

Abstract

Traditional parallel compilers do not effectively parallelize irregular applications because they contain little loop-level parallelism. We explore Speculative Task Parallelism (STP), where tasks are full procedures and entire natural loops. Through profiling and compiler analysis, we find tasks that are speculatively memory- and control-independent of their neighboring code. Via speculative futures, these tasks may be executed in parallel with preceding code when there is a high probability of independence. We estimate the amount of STP in irregular applications by measuring the number of memory-independent instructions these tasks expose. We find that 7 to 22% of dynamic instructions are within memory-independent tasks, depending on assumptions.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. H. Akkary and M. Driscoll. A dynamic multithreading processor. In 31st International Symposium on Microarchitecture, Dec. 1998.

    Google Scholar 

  2. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith. The Tera computer system. 1990 International Conf. on Supercomputing, June 1990.

    Google Scholar 

  3. M. Franklin and G. S. Sohi. ARB: A hardware mechanism for dynamic reordering of memory references. IEEE Transactions on Computers, May 1996.

    Google Scholar 

  4. D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, and W. W. Hwu. Dynamic memory disambiguation using the memory conict buffer. In Proceedings of the 6th International Conference on Architecture Support for Programming Languages and Operating Systems, Oct. 1994.

    Google Scholar 

  5. L. Gwennap. Intel discloses new IA-64 features. Microprocessor Report, Mar. 8 1999.

    Google Scholar 

  6. L. Hammond, M. Willey, and K. Olukotun. Data speculation support for a chip multiprocessor. ACM SIGPLAN Notices, 33(11):58–69, Nov. 1998.

    Article  Google Scholar 

  7. S. Keckler, W. Dally, D. Maskit, N. Carter, A. Chang, and W. Lee. Exploiting finegrain thread level parallelism on the MIT Multi-ALU processor. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-98), pages 306–317, June 1998.

    Google Scholar 

  8. M. S. Lam and R. P. Wilson. Limits of control ow on parallelism. In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA-92), May 1992.

    Google Scholar 

  9. R. H. Litton, J. A. D. McWha, M. W. Pearson, and J. G. Cleary. Block based execution and task level parallelism. In Australasian Computer Architecture Conference, Feb. 1998.

    Google Scholar 

  10. P. Marcuello and A. Gonzalez. Clustered speculative multithreaded processors. In Proceedings of the [ACM] International Conference on Supercomputing, June 1999.

    Google Scholar 

  11. P. Marcuello and A. Gonzalez. Exploiting speculative thread-level parallelism on a SMT processor. In Proceedings of the International Conference on High Performance Computing and Networking, April 1999.

    Google Scholar 

  12. A. Moshovos, S. E. Breach, T. N. Vijaykumar, and G. S. Sohi. Dynamic speculation and synchronization of data dependences. In Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA-97), June 1997.

    Google Scholar 

  13. S. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publ., San Francisco, 1997.

    Google Scholar 

  14. J. T. Oplinger, D. L. Heine, and M. S. Lam. In search of speculative threadlevel parallelism. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT99), October 1999.

    Google Scholar 

  15. J. T. Oplinger, D. L. Heine, S. Liao, B. A. Nayfeh, M. S. Lam, and K. Olukotun. Software and hardware for exploiting speculative parallelism with a multiprocessor. Technical Report CSL-TR-97-715, Stanford University, Computer Systems Laboratory, 1997.

    Google Scholar 

  16. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-95), June 1995.

    Google Scholar 

  17. A. Srivastava and A. Eustace. ATOM: A system for building customized program analysis tools. Research Report 94.2, COMPAQ Western Research Laboratory, 1994.

    Google Scholar 

  18. J. G. Steffan and T. C. Mowry. The potential of using thread-level data speculation to facilitate automatic parallelization. In Proceedings of the 4th International Symposium on High-Performance Computer Architecture, Feb. 1998.

    Google Scholar 

  19. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-95), June 1995.

    Google Scholar 

  20. T. N. Vijaykumar and G. S. Sohi. Task selection for a multiscalar processor. In 31st International Symposium on Microarchitecture, Dec. 1998.

    Google Scholar 

  21. S. Wallace, B. Calder, and D. Tullsen. Threaded multiple path execution. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-98), June 1998.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of California, San Diego La Jolla, CA 92093-0114, USA

    Barbara Kreaseck, Dean Tullsen & Brad Calder

Authors
  1. Barbara Kreaseck
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dean Tullsen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Brad Calder
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Departamento de Arquitectura de Computadores, Universidad Politecnica de Catalunya, Spain

    Mateo Valero

  2. Department of Information and Computer Sciences, Nara Women’s University, Japan

    Kazuki Joe

  3. Institute of Industrial Science Center for Conceptual Information Processing Research, University of Tokyo, Japan

    Masaru Kitsuregawa

  4. Graduate School of Engineering Electrical Engineering Department, University of Tokyo, Japan

    Hidehiko Tanaka

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Kreaseck, B., Tullsen, D., Calder, B. (2000). Limits of Task-based Parallelism in Irregular Applications. In: Valero, M., Joe, K., Kitsuregawa, M., Tanaka, H. (eds) High Performance Computing. ISHPC 2000. Lecture Notes in Computer Science, vol 1940. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39999-2_6

Download citation

  • DOI: https://doi.org/10.1007/3-540-39999-2_6

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41128-4

  • Online ISBN: 978-3-540-39999-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation