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Multi-Processor Computer System Having Low Power Consumption

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Power-Aware Computer Systems (PACS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2325))

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Abstract

We propose to improve battery life in pervasive devices by using multiple processors that trade off computing capacity for improved energy-per-cycle (EPC) efficiency. A separate scheduler circuit intercepts interrupts and schedules execution to minimize overall energy consumption. To facilitate this operation, software tasks are compiled and profiled for execution on multiple processors so that task requirements to computing capacities may be evaluated realistically to satisfy system requirements and task response time. We propose a simple model for estimating the EPC for each processor. To optimize energy consumption, processors are designed to satisfy a particular usage model. Thus, the particular task suite that is anticipated to run on the device, in conjunction with user expectations to software reaction times, governs the design point of each processor. We show that the battery life of a wearable device may be extended by a factor 3–18 depending on users activity.

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© 2003 Springer-Verlag Berlin Heidelberg

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Olsen, C.M., Morrow, L.A. (2003). Multi-Processor Computer System Having Low Power Consumption. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_4

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  • DOI: https://doi.org/10.1007/3-540-36612-1_4

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-01028-9

  • Online ISBN: 978-3-540-36612-6

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