Advertisement

GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages

  • Rolf Drechsler
  • Nicole Drechsler
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2611)

Abstract

Evolutionary Algorithms (EAs) have been proposed as a very powerful heuristic optimization technique to solve complex problems. Many case studies have shown that they work very efficient on a large set of problems, but in general the high qualities can only be obtained by high run time costs. In the past several approaches based on parallel implementations have been studied to speed up EAs. In this paper we present a technique for the implementation of EAs in hardware based on a the concept of reusable modules. These modules are described in a Hardware Description Language (HDL). The resulting “hardware EA” can be directly synthesized and mapped to Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs). This approach finds direct application in signal processing, where hardware implementations are often needed to meet the run time requirements of a real-time system. In our prototype implementation we used VHDL and synthesized an EA for solving the OneMax problem. Simulation results show the feasibility of the approach. Due to the use of a standard HDL, the components can be reused in the form of a library.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    R. Drechsler, Evolutionary Algorithms for VLSI CAD, Kluwer Academic Publisher, 1998Google Scholar
  2. 2.
    P. Mazumder and E. Rudnick, Genetic Algorithms for VLSI Design, Layout & Test Automation, Prentice Hall, 1998Google Scholar
  3. 3.
    M. Erba, R. Rossi, V. Liberali and A. Tettamanzi, An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters, EuroGP, LNCS 2038, pp. 36–50, 2001Google Scholar
  4. 4.
    R. Drechsler and N. Drechsler, Evolutionary Algorithms for Embedded System Design, Kluwer Academic Publisher, 2002Google Scholar
  5. 5.
    E. Cantu-Paz, Efficient and Accurate Parallel Genetic Algorithms, Kluwer Academic Publisher, 2000Google Scholar
  6. 6.
    S. Koizumi, S. Wakabayashi, T. Koide, K. Fujiwara, N. Imura, A RISC Processor for High-Speed Execution of Genetic Algorithms, GECCO, pp. 1338–1345, 2001Google Scholar
  7. 7.
    R. Lipsett, C.F. Schaefer and C. Ussery, VHDL: Hardware Description and Design, Kluwer Academic Publishers, 1989Google Scholar
  8. 8.
    D. Perry, VHDL, McGraw Hill, 1998Google Scholar
  9. 9.
    M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Kluwer Academic Publishers, 1999Google Scholar
  10. 10.
    H. Shibata and N. Fujii, Analog Circuit Synthesis Based on Reuse of Topological Features of Prototype Circuits, GECCO, pp. 1205–1212, 2001Google Scholar
  11. 11.
    N. Göckel, R. Drechsler and B. Becker, GAME: A Software Environment for Using Genetic Algorithms in Circuit Design, Applications of Computer Systems, 240–247, 1997Google Scholar
  12. 12.
    J.H. Holland, Adaption in Natural and Artificial Systems, The University of Michigan Press, Ann Arbor, MI, 1975zbMATHGoogle Scholar
  13. 13.
    I. Rechenberg, Evolutionsstrategie, Frommann-Holzboog, 1973Google Scholar
  14. 14.
    T. Bäck, Evolutionary Algorithms in Theory and Practice, Oxford University Press, 1996Google Scholar
  15. 15.
    J. Koza, Genetic Programming-On the Programming of Computers by means of Natural Selection, MIT Press, 1992Google Scholar
  16. 16.
    L. Davis, Handbook of Genetic Algorithms, van Nostrand Reinhold, New York, 1991Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Rolf Drechsler
    • 1
  • Nicole Drechsler
    • 1
  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany

Personalised recommendations