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A Note on Designing Logical Circuits Using SAT

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Evolvable Systems: From Biology to Hardware (ICES 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2606))

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Abstract

We present a systematic procedure to synthesise and minimise digital circuits using propositional satisfiability. After encoding the truth table into a canonical sum of at most k different products, we seek its minimal satisfiable representation. We show how to use an interesting local search landscape for this minimisation. This approach can be very useful since we can generate exact minimal solutions within reasonably computational resources.

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Author information

Authors and Affiliations

  1. Max-Planck-Institute, Heisenbergstraße 35Q7, D-70569, Stuttgart, Germany

    Giovani Gomez Estrada

Authors
  1. Giovani Gomez Estrada
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Editor information

Editors and Affiliations

  1. The Department of Electronics, The University of York, YO10 5DD, Heslington, York, United Kingdom

    AAndy M. Tyrrell

  2. Department of Computer and Information Science, The Norwegian University of Science and Technology, Sem Sælands Vei, 7491, Trondheim, Norway

    Pauline C. Haddow

  3. Department of Informatics, University of Oslo, P.O. Box 1080, 0316, Blindern, Oslo, Norway

    Jim Torresen

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© 2003 Springer-Verlag Berlin Heidelberg

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Estrada, G.G. (2003). A Note on Designing Logical Circuits Using SAT. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds) Evolvable Systems: From Biology to Hardware. ICES 2003. Lecture Notes in Computer Science, vol 2606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36553-2_37

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  • DOI: https://doi.org/10.1007/3-540-36553-2_37

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00730-2

  • Online ISBN: 978-3-540-36553-2

  • eBook Packages: Springer Book Archive

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