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Use of Particle Swarm Optimization to Design Combinational Logic Circuits

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2606))

Abstract

This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gatelevel. The proposed algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.

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References

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© 2003 Springer-Verlag Berlin Heidelberg

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Coello Coello, C.A., Luna, E.H., Aguirre, A.H. (2003). Use of Particle Swarm Optimization to Design Combinational Logic Circuits. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds) Evolvable Systems: From Biology to Hardware. ICES 2003. Lecture Notes in Computer Science, vol 2606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36553-2_36

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  • DOI: https://doi.org/10.1007/3-540-36553-2_36

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00730-2

  • Online ISBN: 978-3-540-36553-2

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