General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies

Abstract

Accurate models are needed for understanding the biological neuron in its totality. The need for these accurate models is in a evolvable system like a Brainy Processor, understanding unexplored functionality of the brain and fault simulation of the different cortex regions. The accuracy of the model increases computational complexity. Existing software simulators would be extremely slow in terms of performance for large number of neurons. General-purpose processors would have architecture unsuitable to tackle the heavy floating point computation involved in modeling more accurate neuronal assembly models. To overcome this problem, quite a few ASIC chips to simulate simple neural models like (Leaky integrate and fire, Spiking neuron, Hodgkin and Huxley) have been developed. The ASIC architectures proposed are only for simple neuron models where several characteristics are disregarded to lessen hardware complexity. Suggesting ASIC chips for every type of neuronal assembly would be cost prohibitive. To deal with hardware complexity and different classes of neuronal assembly, a programmable hardware unit or in a wider sense an instruction driven general-purpose processor architecture is proposed. The functional units of this architecture are tailored to evaluate complex stochastic neuronal assembly models.