Performance Driven Routing in Distributed Environment

  • Arpan Singha
  • Rajat K. Pal
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2571)


As fabrication technology advances, devices and interconnection wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Work on routing channels with reduced crosstalk is a very important area of current research [3],[10]. We know that the crosstalk minimization problem in the reserved two-layer Manhattan routing model is NP-complete, even for the channels without any vertical constraints. Since minimizing crosstalk is NP-complete, several polynomial time heuristic algorithms for reducing crosstalk have been developed [8],[9], [15]. All the ideas that are introduced as heuristics are basically sequential in nature. In this paper we have developed two efficient heuristics to compute reduced crosstalk routing solutions in a distributed computing environment. Our proposed heuristics are much better in computational complexity than the existing sequential versions of the algorithms developed in [9], [15].


Blank Space Wire Segment Distribute Computing Environment Parallel Random Access Machine Total Span 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Batcher, K.E.: Sorting Networks and their Applications, Proc. of the AFIPS Spring Joint Computer Conf., Vol. 32, AFIPS Press, Reston, VA (1968) 307–314. Reprinted in: Wu, C.L. and Feng, T.S. (eds.): Interconnection Networks for Parallel and Distributed Processing, IEEE Computer Society (1984) 576-583.Google Scholar
  2. 2.
    Chen, Y.K., Liu, M.L.: Three-Layer Channel Routing, IEEE Trans. on CAD of Integrated Circuits and Systems 3 (1984) 156–163.CrossRefGoogle Scholar
  3. 3.
    Gao, T., Liu, C.L.: Minimum Crosstalk Channel Routing, Proc. of IEEE Int. Conf. on Computer-Aided Design (1993) 692–696.Google Scholar
  4. 4.
    Hashimoto, A., Stevens, J.: Wire Routing by Optimizing Channel Assignment within Large Apertures, Proc. of 8th ACM Design Automation Workshop (1971) 155–169.Google Scholar
  5. 5.
    Ho, T.-T., Iyengar, S.S., Zheng, S.-Q.: A General Greedy Channel Routing Algorithm, IEEE Trans. on CAD of Integrated Circuits and Systems 10 (1991) 204–211.CrossRefGoogle Scholar
  6. 6.
    Hwang, K.: Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, Inc., New York (1993).Google Scholar
  7. 7.
    LaPaugh, A.S.: Algorithms for Integrated Circuit Layout: An Analytic Approach, Ph.D. thesis, Lab. for Computer Sc., MIT, Cambridge (1980).Google Scholar
  8. 8.
    Pal, A., Dam, B., Sadhu, S., Pal, R.K.: Performance Driven Physical Synthesis, Communicated to an International VLSI Journal (2002).Google Scholar
  9. 9.
    Pal, A., Singha, A., Ghosh, S., Pal, R.K.: Crosstalk Minimization in Two-Layer Channel Routing, Accepted in 17th IEEE Region 10 Int. Conf. on “Computers, Communications, Control and Power Engineering” (TENCON’02), to be held in Beijing, China (2002).Google Scholar
  10. 10.
    Pal, R.K.: Multi-Layer Channel Routing: Complexity and Algorithms, Narosa Publishing House, New Delhi (2000). Also published from CRC Press, Boca Raton, USA (2000) and Alpha Sc. Int. Ltd., UK (2000).zbMATHGoogle Scholar
  11. 11.
    Pal, R.K., Datta, A.K., Pal, S.P., Pal, A.: Resolving Horizontal Constraints and Minimizing Net Wire Length for Multi-Layer Channel Routing, Proc. of IEEE Region 10’s 8th Annual Int. Conf. on “Computer, Communication, Control and Engineering” (TENCON’93) 1 (1993) 569–573.Google Scholar
  12. 12.
    Pal, R.K., Datta, A.K., Pal, S.P., Das, M.M., Pal, A.: A general Graph Theoretic Framework for Multi-Layer Channel Routing, Proc. of 8th VSI/IEEE Int. Conf. on VLSI Design (1995) 202–207.Google Scholar
  13. 13.
    Quinn, M.J.: Parallel Computing: Theory and Practice, Second Edition, McGraw-Hill, Inc., New York, USA (1994).Google Scholar
  14. 14.
    Schaper, G.A.: Multi-Layer Channel Routing, Ph.D. thesis, Dept. of Computer Sc., Univ. of Central Florida, Orlando (1989).Google Scholar
  15. 15.
    Singha, A., Ghosh, S., Pal, A., Pal, R.K.: High Performance Routing for VLSI Circuit Synthesis, Proc. of 6th VLSI Design and Test Workshops (VDAT’02) (2002) 348–351.Google Scholar
  16. 16.
    Szymanski, T.G.: Dogleg Channel Routing is NP-Complete, IEEE Trans. on CAD of Integrated Circuits and Systems 4 (1985) 31–41.CrossRefGoogle Scholar
  17. 17.
    Yoshimura, T., Kuh, E.S.: Efficient Algorithms for Channel Routing, IEEE Trans. on CAD of Integrated Circuits and Systems 1 (1982) 25–35.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Arpan Singha
    • 1
  • Rajat K. Pal
    • 1
  1. 1.Department of Computer Science and EngineeringUniversity of CalcuttaKolkataIndia

Personalised recommendations