Advertisement

A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs

  • Prithviraj Banerjee
  • Malay Haldar
  • Anshuman Nayak
  • Victor Kim
  • Debabrata Bagchi
  • Satrajit Pal
  • Nikhil Tripathi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2571)

Abstract

This paper describes how fine grain parallelism can be exploited using a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto FPGAs. The paper describes how powerful directives are used to provide high-level architectural tradeoffs by exploiting fine grain parallelism, pipelining, memory mapping and tiling for the DSP designer. Experimental results are reported with the AccelFPGA version 1.4 compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II FPGAs.

Keywords

Digital Signal Processing Finite Impulse Response Finite Impulse Response Filter Register Transfer Level Hardware Description Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Adelante Technologies, ART Builder, http://www.adelantetechnologies.com
  2. 2.
    Altera, Stratix Datasheet, http://www.altera.com
  3. 3.
    Celoxica Corp, Handle C Design Language, http://www.celoxica.com
  4. 4.
    C Level Design, System Compiler: Compiling ANSI C/C++ to Synthesis-ready HDL, http://www.cleveldesign.com
  5. 5.
    CynApps Suite. Cynthesis Applications for Higher Level Design. http://www.cynapps.com
  6. 6.
    G. DeMicheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994Google Scholar
  7. 7.
    Esterel-C Language (ECL). Cadence website. http://www.cadence.com
  8. 8.
    M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, “A System for Synthesizing Optimized FPGA Hardware from MATLAB,” Proc. International Conference on Computer Aided Design, San Jose, CA, November 2001, See also http://www.ece.northwestern.edu/cpdc/Match/Match.html.
  9. 9.
    Mathworks Corp, MATLAB Technical Computing Environment, http://www.mathworks.com
  10. 10.
    De Micheli, G. Ku D. Mailhot, F. Truong T. The Olympus Synthesis System for Digital Design. IEEE Design amp; Test of Computers 1990.Google Scholar
  11. 11.
    Overview of the Open SystemC Initiative. SystemC website. http://www.systemc.org
  12. 12.
    Synopsys Corp, Behavioral Compiler Datasheet, http://www.synopsys.com
  13. 13.
    Synplicity. Synplify Pro Datasheet, http://www.synplicity.com.
  14. 14.
    Xilinx, Virtex II Datasheet, http://www.xilinx.com
  15. 15.
    Xilinx, System Generator Datasheet, http://www.xilinx.com
  16. 16.
    Altera, DSP Builder Datasheet, http://www.altera.com
  17. 17.
    Texas Instruments, VelocTI C6000 Architecture Description, http://www.ti.com
  18. 18.
    Phillips Corporation, Trimedia Architecture Description, http://www.phillips.com
  19. 19.
    Motorola Corporation, STARCORE Datasheet, http://www.motorola.com

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Prithviraj Banerjee
    • 1
  • Malay Haldar
    • 1
  • Anshuman Nayak
    • 1
  • Victor Kim
    • 1
  • Debabrata Bagchi
    • 1
  • Satrajit Pal
    • 1
  • Nikhil Tripathi
    • 1
  1. 1.AccelChip, Inc.Schaumburg

Personalised recommendations