Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors

  • Mohan G. Kabadi
  • Natarajan Kannan
  • Palanidaran Chidambaram
  • Suriya Narayanan
  • M. Subramanian
  • Ranjani Parthasarathi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2552)


Both power and performance are important design parameters of the present day processors. This paper explores an integrated software and circuit level technique to reduce leakage power in L1 instruction caches of high performance microprocessors, by eliminating basic blocks from the cache, as soon as they are dead. The effect of this dead block elimination in cache on both the power consumption of the I-cache and the performance of the processor is studied. Identification of basic blocks is done by the compiler from the control flow graph of the program. This information is conveyed to the processor, by annotating the first instruction of selected basic blocks. During execution, the blocks that are not needed further are traced and invalidated and the lines occupied by them are turned off. This mechanism yields an average of about 5% to 16% reduction, in the energy consumed for different sizes of I-cache, for a set of the SPEC CPU 2000 benchmarks [16], without any performance degradation.


Basic Block Power Saving Cache Size Cache Line Benchmark Suite 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Mohan G. Kabadi
    • 1
  • Natarajan Kannan
    • 1
  • Palanidaran Chidambaram
    • 1
  • Suriya Narayanan
    • 1
  • M. Subramanian
    • 1
  • Ranjani Parthasarathi
    • 1
  1. 1.School of Computer Science and Engineering Anna UniversityChennaiIndia

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