Accelerating the CKY Parsing Using FPGAs

  • Jacir L. Bordim
  • Yasuaki Ito
  • Koji Nakano
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2552)


The main contribution of this paper is to present an FPGAbased implementation of an instance-specific hardware which accelerates the CKY (Cook-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines if G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The created source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm. Hence, we believe that our approach is a promising solution for the CKY parsing.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Jacir L. Bordim
    • 1
  • Yasuaki Ito
    • 1
  • Koji Nakano
    • 1
  1. 1.School of Information ScienceJapan Advanced Institute of Science and TechnologyTatsunokuchiJapan

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