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Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing

  • Rama Sangireddy
  • Huesung Kim
  • Arun K. Somani
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2552)

Abstract

The demand for higher computing power and thus more onchip computing resources is ever increasing. The size of on-chip cache memory has also been consistently increasing. To efficiently utilize silicon real-estate on the chip, a part of L1 data cache is designed as a Reconfigurable Functional Cache (RFC), that can be configured to perform a selective core function in the media application whenever higher computing capability is required. The idea of Adaptive Balanced Computing architecture was developed, where the RFC module is used as a coprocessor controlled by main processor. Initial results have proved that ABC architecture provides speedups ranging from 1.04x to 5.0x for various media applications. In this paper, we address the impact of RFC on cache access time and energy dissipation. We show that reduced number of cache accesses and lesser utilization of other on-chip resources will result in energy savings of up to 60% for MPEG decoding, and in the range of 10% to 20% for various other multimedia applications.

Keywords

Power Dissipation Access Time Cache Size Data Cache Line Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Rama Sangireddy
    • 1
  • Huesung Kim
    • 1
  • Arun K. Somani
    • 1
  1. 1.Dependable Computing amp; Networking Laboratory, Department of Electrical and Computer EngineeringIowa State UniversityAmesUSA

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