Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing

  • Rama Sangireddy
  • Huesung Kim
  • Arun K. Somani
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2552)


The demand for higher computing power and thus more onchip computing resources is ever increasing. The size of on-chip cache memory has also been consistently increasing. To efficiently utilize silicon real-estate on the chip, a part of L1 data cache is designed as a Reconfigurable Functional Cache (RFC), that can be configured to perform a selective core function in the media application whenever higher computing capability is required. The idea of Adaptive Balanced Computing architecture was developed, where the RFC module is used as a coprocessor controlled by main processor. Initial results have proved that ABC architecture provides speedups ranging from 1.04x to 5.0x for various media applications. In this paper, we address the impact of RFC on cache access time and energy dissipation. We show that reduced number of cache accesses and lesser utilization of other on-chip resources will result in energy savings of up to 60% for MPEG decoding, and in the range of 10% to 20% for various other multimedia applications.


Power Dissipation Access Time Cache Size Data Cache Line Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    A. DeHon, “The Density Advantage of Configurable Computing”, IEEE Computer, Volume: 33, Issue: 4, April 2000, pp. 41–49 124Google Scholar
  2. [2]
    H. Kim, A.K. Somani, and A. Tyagi, “A Reconfigurable Multifunction Computing Cache Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Issue:4, August 2001, pp. 509–523. 125, 126Google Scholar
  3. [3]
    Huesung Kim, “Towards Adaptive Balanced Computing (ABC) Using Reconfigurable Functional Caches (RFCs)”, Ph. D. Dissertation, Dept. of Electrical and Computer Engineering, Iowa State University, July 2001. Available at: 125, 126, 127, 129, 130
  4. [4]
    Tomohisa Wada, Suresh Rajan, and Steven A. Przybylski, “An Analytical Access Time Model for On-Chip Cache Memories”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, August 1992, pp. 1147–1156. 126CrossRefGoogle Scholar
  5. [5]
    S.E. Wilton and N.P. Jouppi, “An Enhanced Access and Cycle Time Model for On-chip Caches”, DEC WRL Research 93/5, July 1994. 126, 128Google Scholar
  6. [6]
    P. Shivakumar and N.P. Jouppi, “CACTI3.0: An Integrated Cache Timing, Power, and Area Power Model”, DEC WRL Research 2001/2, August 2001. 126, 128Google Scholar
  7. [7]
    Chunho Lee, M. Potkonjak and W. H. Mangione-Smith, “MediaBench: a tool for evaluating and synthesizing multimedia and communications systems”, Proc. Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997, pp. 330–335. 127Google Scholar
  8. [9]
    Doug Burger and Todd M. Austin, “The SimpleScalar Tool Set, Version 2.0”, Computer Sciences Department Technical report # 1342, University of Wisconsin-Madison, June 1997. 129Google Scholar
  9. [10]
    D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: AF ramework for Architectural-Level Power Analysis and Optimizations”, Proc. 27th International Symposium on Computer Architecture, 2000, pp. 83–94. 131Google Scholar
  10. [11]
    R. Joseph and M. Martonosi, “Run-Time Power Estimation in High Performance Microprocessors”, Proc. International Symposium on Low Power Electronics and Design, 2001, pp. 135–140. 131Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Rama Sangireddy
    • 1
  • Huesung Kim
    • 1
  • Arun K. Somani
    • 1
  1. 1.Dependable Computing amp; Networking Laboratory, Department of Electrical and Computer EngineeringIowa State UniversityAmesUSA

Personalised recommendations