Abstract
This paper presents a methodology for the design of application-specific multiprocessor systems. The methodology, named AIM, guides a designer to select the right heterogeneous architecture starting from a set of target applications. The methodology distinguishes between applications and architectures that are modeled as Kahn Process Networks and cycle-accurate bit-true models, respectively. A gradual mapping of applications over architectures is defined to analyze the performance of the resulting system by simulation. As a consequence, functionally complete system is always available with the designer without the overwhelming issues related with the multiprocessor architectures. The described methodology is illustrated through the design of a multiprocessor architecture for an MPEG-1 audio decoder application.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Peter, P., Stolberg, H.J.: VLSI implementations of image and video multimedia processing systems. IEEE Trans. on Circuits and Systems for Video technology, Vol. 8. (1998) 878–891
Kienhuis, A.C.J.: Design Space Exploration of Streambased Dataflow Architectures-Methods and Tools, Ph.D. thesis, Delft University of Technology (1999)
Kahn, G.: The semantics of a simple language for parallel programming, Proc. of the IFIP Congress 74, North Holland Publishing Co. (1974)
Lee, E.A., David, G.M.,: Synchronous data flow. Proc. of the IEEE, Vol. 75. (1987) 1235–1245
Lee, E.A., Parks, T.M.,: Dataflow process networks. Proc. of the IEEE, Vol. 83. (1995) 773–799
Joseph, B., Ha, S., Lee, E.A., David, G.M.: Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int. Journal of Computer Simulation, Special issue on Simulation Software Development. (1992)
Chang, W., Ha, S., Lee, E.A.,: Heterogeneous simulation-mixing discrete event models with dataflow. Journal of VLSI Processing, Vol. 15. (1997) 127–144
Kung, H.T.: Why systolic architectures?. IEEE Computer, Vol. 15. (1982)
Kung, H.T., Leiserson, C.E.: Systolic arrays (for VLSI). Sparse Matrix Symposium, SIAM (1978) 256–282
Kung, S.Y., Arun, K.S., Gal-Ezer, R.J., Rao, D.V. B.: Wavefront array processor: language, architecture, and applications. IEEE Trans. on Computers, Special Issue on Parallel and Distributed Computer, Vol. 31. (1982) 1054–1066
Michele, G.M., Sami, M.: Hardware/Software Co-Design. Series E: Applied Sciences, NATO ASI Series, Vol. 310. (1996)
Chen, D.C., Rabaey, J.M.: Paddi: Programmable arithmetic devices for digital signal processing. Proc. of VLSI Signal Processing IV (1990) 240–249
Lippens, P.E.R., van Meerbergen, J.L., van der Werf, A., Verhaegh, W.F.J., McSweeney, B.T., Huisken, J.O., McArdle, O.P.: PHIDEO: A silicon compiler for high speed algorithms. Proc. EDAC (1991) 436–441
Gupta R.K., Liao, S.Y.: Using a programming language for digital system design. IEEE Design amp; Test of Computers,Vol. 14. (1997) 72–80
Hein, C., Pridgen, J., Kline, W.: RASSP: virtual prototyping of DSP systems. Proc. DAC (1997)
Klenke, R.H., Meyassed, M., Aylor, J.H., Johnson, B.W., Rao, R., Ghosh, A.: An integrated design environment for performance and dependability analysis. Proc. DAC (1997)
Kahn, G., MacQueen, D.B.: Coroutines and networks of parallel processes. Proc. of the IFIP Congress 77. North-Holland Publishing Company Co. (1977)
de Kock E.A.: YAPI: Application modeling for signal processing systems.Proc.DAC (2000)
Kruijtzer, W.: TSS: Tool for System Simulation. ISTNewsletter, Philips Internal Publication (1997) 5–7
Benini, L., Micheli, G.D., Macii, E., Sciuto, D., Silvano, C.: Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. IEEE 7th Great Lakes Symposium on VLSI. (1997) 77–82
Stan, M.R., Burleson, W.P.: Bus-Invert Coding for Low-Power I/O. IEEE Trans. on VLSI Systems, Vol. 3. (1995) 49–58
Flynn, D.: AMBA: Enabling Reusable On-Chip Designs”, IEEE Micro (1997)
Klapproth, P.: PRISC Architecture Framework. Philips Internal Publication (1999)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Saif Abrar, S. (2002). High Performance Multiprocessor Architecture Design Methodology for Application-Specific Embedded Systems. In: Sahni, S., Prasanna, V.K., Shukla, U. (eds) High Performance Computing — HiPC 2002. HiPC 2002. Lecture Notes in Computer Science, vol 2552. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36265-7_10
Download citation
DOI: https://doi.org/10.1007/3-540-36265-7_10
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-00303-8
Online ISBN: 978-3-540-36265-4
eBook Packages: Springer Book Archive