Performance Analysis of Asynchronous Circuits Using Markov Chains

  • Peter A. Beerel
  • Aiguo Xie
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2549)


In an increasing number of instances, asynchronous circuit can provide advantages in either performance, power, electromagnetic interference, and/or design time [56], [45], [5], [3]. Asynchronous circuits circumvent the limitations and somewhat rigid design framework associated with global synchronization dictated by a globally distributed clock signal. Instead, asynchronous systems generally consist of a collection of parallel computation processes that synchronize and exchange data through handshaking-based communication. This facilitates pipelining communication across long distances, optimizing for average case behavior, and integrating slow and fast processes.


Markov Chain Sojourn Time State Compression Reachable State Communicate Sequential Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    A. M. Abdel-Moneim and F. W. Leysieffer. Weak lumpability in finite Markov chains. Journal of Applied Probability, 19:685–691, 1982. 329zbMATHCrossRefMathSciNetGoogle Scholar
  2. [2]
    R. I. Bahar, E. A. Frohm, C. M. Gaona, and G. D. Hachtel. Algebraic decision diagrams and their applications. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 188–191, 1993. 327, 329Google Scholar
  3. [3]
    Peter A. Beerel. Asynchronous circuits: An increasing practical design solution. In Proc. of ISQED, 2002. 313Google Scholar
  4. [4]
    W. Belluomini and C. J. Myers. Verification of timed systems using POSETS. In Proc. International Workshop on Computer Aided Verification, pages 403–415, 1998. 314Google Scholar
  5. [5]
    C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223–233, February 1999. 313Google Scholar
  6. [6]
    R. E. Bryant. Graph-based algorithm for boolean function munipulation. IEEE Transactions on Computers, 35, August 1986. 327Google Scholar
  7. [7]
    J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design, 13(4):401–424, April 1994. 328CrossRefGoogle Scholar
  8. [8]
    S. M. Burns. Performance Analysis and Optimization of Asynchronous Circuits. PhD thesis, California Institute of Technology, 1991. 314Google Scholar
  9. [9]
    T. J. Chaney and C. E. Molnar. Anomalous behavior of synchronizer and arbiter circuits. IEEE Transactions on Computers, C-22(4):421–422, April 1973. 315, 329CrossRefGoogle Scholar
  10. [10]
    K. Cheng and V. D. Agrawal. A partial scan method for sequential circuits and feedback. IEEE Transactions on Computers, 39(4):544–548, April 1990. 330CrossRefGoogle Scholar
  11. [11]
    T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifi-cations. PhD thesis, Massachusetts Institute of Technology, 1987. 314Google Scholar
  12. [12]
    K. L. Chung. Markov Chains with Stationary Transition Probabilities. Springer-Verlag, 1960.Google Scholar
  13. [13]
    Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In XI Conference on Design of Integrated Circuits and Systems, Barcelona, November 1996. 314Google Scholar
  14. [14]
    O. Coudert, J. C. Madre, and C. Berthet. Verifying temporal properties of sequential machines without building their state diagrams. In E. M. Clarke and R. P. Kurshan, editors, Computer-Aided Verification’90, pages 75–84. American Mathematical Society, June 1990. 328Google Scholar
  15. [15]
    Al Davis. A data-driven machine architecure suitable for VLSI implementation. In Proceedings of the Caltech Conference on Very Large Scale Integration, pages 479–494, 1979. 314Google Scholar
  16. [16]
    J. Ebergen and R. Berks. Response time properties of some asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 76–86. IEEE Computer Society Press, April 1997. 314Google Scholar
  17. [17]
    J. C. Ebergen. A formal approach to designing delay-insensitive circuits. Distributed Computing, 3(5):107–119, 1991. 314CrossRefGoogle Scholar
  18. [18]
    M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman and Company, 1979. 330Google Scholar
  19. [19]
    M. R. Greenstreet and K. Steiglitz. Bubbles can make self-timed pipelines fast. Journal of VLSI Signal Processing, 2(3):139–148, November 1990. 315CrossRefGoogle Scholar
  20. [20]
    G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Markovian analysis of large finite state machines. IEEE Transactions on Computer-Aided Design, 15(12):1479–1493, December 1996. 322CrossRefGoogle Scholar
  21. [21]
    Y. Ho and X. Cao. Perturbation analysis of discrete event dynamic systems. Kluwer Academic Publishers, 1991. 329Google Scholar
  22. [22]
    C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall International, UK. LTD., Englewood Cliffs, New Jersey, 1985. 314zbMATHGoogle Scholar
  23. [23]
    M. A. Holliday and M. Y. Vernon. A generalized timed Petri net model for performance analysis. IEEE Transactions on Software Engineering, 13(12):1297–1310, December 1987. 315CrossRefGoogle Scholar
  24. [24]
    H. Hulgaard and S. M. Burns. Bounded delay timing analysis of a class of CSP programs with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 2–11. IEEE Computer Society Press, November 1994. 314Google Scholar
  25. [25]
    H. Hulgaard and S. M. Burns. An algorithm for exact bounds on time separation of events in concurrent systems. IEEE Transactions on Computers, 44(11):1306–1317, November 1995. 314zbMATHCrossRefGoogle Scholar
  26. [26]
    R. M. Karp. A characterization of the minimum cycle mean in a diagraph. Discrete mathematics, 23:309–311, 1978. 314zbMATHMathSciNetGoogle Scholar
  27. [27]
    J. G. Kemeny and J. L. Snell. Finite Markov Chains. Springer, 1976.Google Scholar
  28. [28]
    P. Kudva, G. Gopalakrishnan, E. Brunvand, and V. Akella. Performance analysis and optimization of asynchronous circuits. In Proc. International Conf. Computer Design (ICCD), pages 221–225, October 1994. 315, 318Google Scholar
  29. [29]
    V. G. Kulkarni. Modeling and Analysis of Stochastic Systems. Chapman & Hall, 1995. 322Google Scholar
  30. [30]
    H. J. Kushner. A control problem for a new type of public transportation system, via heavy traffic analysis. In F.P. Kelly and R. J. Williams, editors, The IMA Volumes in Mathematics and Its Applications: Stochastic networks, pages 139–168. Springer-Verlag, 1995. 318Google Scholar
  31. [31]
    M. Ajmone Marsan, G. Balbo, and G. Conte. A Class of Generalized Stochastic Petri Nets.ACM Trans. on Comput. Syst., 12:93–122, May 1984. 315Google Scholar
  32. [32]
    A. J. Martin. Programming in VLSI: from communicating processes to delayinsensitive VLSI circuits. In C. A. R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming, pages 1–64. Addison-Wesley, 1990. 314Google Scholar
  33. [33]
    K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993. 328Google Scholar
  34. [34]
    M. K. Molloy. On the Integration of delay and throughput measures in distributed processing models. PhD thesis, University of California, Los Angeles, 1981. 315Google Scholar
  35. [35]
    M. K. Molloy. Discrete Time Stochastic Petri Nets. IEEE Transactions on Software Engineering, 11:417–423, April 1985. 315Google Scholar
  36. [36]
    C. J. Myers and T. H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106–119, June 1993. 314CrossRefGoogle Scholar
  37. [37]
    S. M. Nowick and D. Dill. “Asynchronous State Machine Synthesis Using a Local Clock”. In International Workshop on Logic Synthesis, 1991. 314Google Scholar
  38. [38]
    S. Park and S. B. Akers. A graph theoretic approach to partial scan design by k-cycle elimination. In Proc. IEEE International Test Conference, pages 303–311, 1992. 330Google Scholar
  39. [39]
    J. L. Peterson. Petri Net Theory and the Modeling of Systems. Prentice Hall, 1981. 314Google Scholar
  40. [40]
    V. D. Ploeg. Preconditioning techniques for large sparse, non-symmetric matrices with arbitrary sparsity patterns. In Proc. IMACS Symposium on Iterative Methods in Linear Algebra, pages 173–179, 1991. 329Google Scholar
  41. [41]
    G. Rubino and B. Sericola. On weak lumpability in Markov chains. Journal of Applied Probability, 26:446–457, 1989. 329zbMATHCrossRefMathSciNetGoogle Scholar
  42. [42]
    G. Rubino and B. Sericola. Sojourn times in finite Markov process. Journal of Applied Probability, 27:744–756, 1989. 323CrossRefMathSciNetGoogle Scholar
  43. [43]
    T. Shiple, R. Hojati, A. Sangiovanni-Vincentelli, and R. K. Brayton. Heuristic minimization of bdds using don’t cares. In Proc. ACM/IEEE Design Automation Conference, pages 225–231, 1994. 329Google Scholar
  44. [44]
    G. W. Smith, Jr. and R. B. Walford. The identification of a minimal feedback vertex set of a directed graph. IEEE Transactions on Circuits and Systems, 22(1):9–15, January 1975. 330CrossRefMathSciNetGoogle Scholar
  45. [45]
    K. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 36(2):217–228, February 2001. 313CrossRefGoogle Scholar
  46. [46]
    G. W. Stewart. Methods of simultaneous iteration for computing invariant subspaces of non-ruminating matrices. Numerical Mathematics, 25:123–136, 1976. 329zbMATHCrossRefGoogle Scholar
  47. [47]
    W. J. Stewart. An Introduction to the Numerical Solution of Markov Chains. Princeton University Press, 1994.Google Scholar
  48. [48]
    S. H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, 1969. (re-issued by R.E. Krieger, Malabar, 1983). 314Google Scholar
  49. [49]
    H. J. M. Veendrick. The behavior of flip-flops used as synchronizers and prediction of their falure. IEEE Journal of Solid-State Circuits, SC-15(2):169–176, April 1980. 329CrossRefGoogle Scholar
  50. [50]
    A. Xie and P. A. Beerel. Symbolic techniques for performance analysis of asynchronous systems based on average time separation of events. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 64–75. IEEE Computer Society Press, April 1997. 314, 318, 321, 338Google Scholar
  51. [51]
    A. Xie and P. A. Beerel. Efficient state classification of finite state Markov chains. IEEE Transactions on Computer-Aided Design, 17(12):1334–1338, December 1998. 314, 322, 327CrossRefGoogle Scholar
  52. [52]
    A. Xie and P. A. Beerel. Accelerating Markovian analysis of asynchronous systems using state compression. IEEE Transactions on Computer-Aided Design, 18(7):869–888, July 1999. 314, 327, 340CrossRefGoogle Scholar
  53. [53]
    A. Xie and P. A. Beerel. Performance analysis of asynchronous circuits and systems using stochastic timed Petri nets. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 239–268. Kluwer Academic Publishers, March 2000. 314Google Scholar
  54. [54]
    A. Xie, S. Kim, and P. A. Beerel. Bounding average time separation of events in stochastic timed Petri nets with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), April 1999. 314Google Scholar
  55. [55]
    Aiguo Xie. Performance Analysis of Asynchronous Circuits and Systems. PhD thesis, University of Southern California, August 1999. 321, 322, 324, 325Google Scholar
  56. [56]
    K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, and J. Arceo. A low-controloverhead asynchronous differential equation solver. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 210–223. IEEE Computer Society Press, April 1997. 313, 334, 335Google Scholar
  57. [57]
    K. Y. Yun, D. L. Dill, and S. M. Nowick. Synthesis of 3D asynchronous state machines. In Proc. International Conf. Computer Design (ICCD), pages 346–350. IEEE Computer Society Press, October 1992. 314Google Scholar
  58. [58]
    K. Y. Yun and R. P. Donohue. Pausible clocking: A first step toward heterogeneous systems. In Proc. International Conf. Computer Design (ICCD), pages 118–123. IEEE Computer Society Press, October 1996. 336Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Peter A. Beerel
    • 1
  • Aiguo Xie
    • 2
  1. 1.EE Department, Systems DivisionUniversity of Southern CaliforniaLos Angeles
  2. 2.Fulcrum MicrosystemsCalabasas Hills

Personalised recommendations