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Concurrency and Hardware Design pp 313–343Cite as

Performance Analysis of Asynchronous Circuits Using Markov Chains

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2549))

Abstract

In an increasing number of instances, asynchronous circuit can provide advantages in either performance, power, electromagnetic interference, and/or design time [56], [45], [5], [3]. Asynchronous circuits circumvent the limitations and somewhat rigid design framework associated with global synchronization dictated by a globally distributed clock signal. Instead, asynchronous systems generally consist of a collection of parallel computation processes that synchronize and exchange data through handshaking-based communication. This facilitates pipelining communication across long distances, optimizing for average case behavior, and integrating slow and fast processes.

This research was funded in part by a gift from TRW, a large-scale NSF ITR Award No. CCR-00-86036, and a NSF Award No. CCR-98-12164.

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References

  1. A. M. Abdel-Moneim and F. W. Leysieffer. Weak lumpability in finite Markov chains. Journal of Applied Probability, 19:685–691, 1982. 329

    Article  MATH  MathSciNet  Google Scholar 

  2. R. I. Bahar, E. A. Frohm, C. M. Gaona, and G. D. Hachtel. Algebraic decision diagrams and their applications. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 188–191, 1993. 327, 329

    Google Scholar 

  3. Peter A. Beerel. Asynchronous circuits: An increasing practical design solution. In Proc. of ISQED, 2002. 313

    Google Scholar 

  4. W. Belluomini and C. J. Myers. Verification of timed systems using POSETS. In Proc. International Workshop on Computer Aided Verification, pages 403–415, 1998. 314

    Google Scholar 

  5. C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223–233, February 1999. 313

    Google Scholar 

  6. R. E. Bryant. Graph-based algorithm for boolean function munipulation. IEEE Transactions on Computers, 35, August 1986. 327

    Google Scholar 

  7. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design, 13(4):401–424, April 1994. 328

    Article  Google Scholar 

  8. S. M. Burns. Performance Analysis and Optimization of Asynchronous Circuits. PhD thesis, California Institute of Technology, 1991. 314

    Google Scholar 

  9. T. J. Chaney and C. E. Molnar. Anomalous behavior of synchronizer and arbiter circuits. IEEE Transactions on Computers, C-22(4):421–422, April 1973. 315, 329

    Article  Google Scholar 

  10. K. Cheng and V. D. Agrawal. A partial scan method for sequential circuits and feedback. IEEE Transactions on Computers, 39(4):544–548, April 1990. 330

    Article  Google Scholar 

  11. T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifi-cations. PhD thesis, Massachusetts Institute of Technology, 1987. 314

    Google Scholar 

  12. K. L. Chung. Markov Chains with Stationary Transition Probabilities. Springer-Verlag, 1960.

    Google Scholar 

  13. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In XI Conference on Design of Integrated Circuits and Systems, Barcelona, November 1996. 314

    Google Scholar 

  14. O. Coudert, J. C. Madre, and C. Berthet. Verifying temporal properties of sequential machines without building their state diagrams. In E. M. Clarke and R. P. Kurshan, editors, Computer-Aided Verification’90, pages 75–84. American Mathematical Society, June 1990. 328

    Google Scholar 

  15. Al Davis. A data-driven machine architecure suitable for VLSI implementation. In Proceedings of the Caltech Conference on Very Large Scale Integration, pages 479–494, 1979. 314

    Google Scholar 

  16. J. Ebergen and R. Berks. Response time properties of some asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 76–86. IEEE Computer Society Press, April 1997. 314

    Google Scholar 

  17. J. C. Ebergen. A formal approach to designing delay-insensitive circuits. Distributed Computing, 3(5):107–119, 1991. 314

    Article  Google Scholar 

  18. M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman and Company, 1979. 330

    Google Scholar 

  19. M. R. Greenstreet and K. Steiglitz. Bubbles can make self-timed pipelines fast. Journal of VLSI Signal Processing, 2(3):139–148, November 1990. 315

    Article  Google Scholar 

  20. G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Markovian analysis of large finite state machines. IEEE Transactions on Computer-Aided Design, 15(12):1479–1493, December 1996. 322

    Article  Google Scholar 

  21. Y. Ho and X. Cao. Perturbation analysis of discrete event dynamic systems. Kluwer Academic Publishers, 1991. 329

    Google Scholar 

  22. C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall International, UK. LTD., Englewood Cliffs, New Jersey, 1985. 314

    MATH  Google Scholar 

  23. M. A. Holliday and M. Y. Vernon. A generalized timed Petri net model for performance analysis. IEEE Transactions on Software Engineering, 13(12):1297–1310, December 1987. 315

    Article  Google Scholar 

  24. H. Hulgaard and S. M. Burns. Bounded delay timing analysis of a class of CSP programs with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 2–11. IEEE Computer Society Press, November 1994. 314

    Google Scholar 

  25. H. Hulgaard and S. M. Burns. An algorithm for exact bounds on time separation of events in concurrent systems. IEEE Transactions on Computers, 44(11):1306–1317, November 1995. 314

    Article  MATH  Google Scholar 

  26. R. M. Karp. A characterization of the minimum cycle mean in a diagraph. Discrete mathematics, 23:309–311, 1978. 314

    MATH  MathSciNet  Google Scholar 

  27. J. G. Kemeny and J. L. Snell. Finite Markov Chains. Springer, 1976.

    Google Scholar 

  28. P. Kudva, G. Gopalakrishnan, E. Brunvand, and V. Akella. Performance analysis and optimization of asynchronous circuits. In Proc. International Conf. Computer Design (ICCD), pages 221–225, October 1994. 315, 318

    Google Scholar 

  29. V. G. Kulkarni. Modeling and Analysis of Stochastic Systems. Chapman & Hall, 1995. 322

    Google Scholar 

  30. H. J. Kushner. A control problem for a new type of public transportation system, via heavy traffic analysis. In F.P. Kelly and R. J. Williams, editors, The IMA Volumes in Mathematics and Its Applications: Stochastic networks, pages 139–168. Springer-Verlag, 1995. 318

    Google Scholar 

  31. M. Ajmone Marsan, G. Balbo, and G. Conte. A Class of Generalized Stochastic Petri Nets.ACM Trans. on Comput. Syst., 12:93–122, May 1984. 315

    Google Scholar 

  32. A. J. Martin. Programming in VLSI: from communicating processes to delayinsensitive VLSI circuits. In C. A. R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming, pages 1–64. Addison-Wesley, 1990. 314

    Google Scholar 

  33. K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993. 328

    Google Scholar 

  34. M. K. Molloy. On the Integration of delay and throughput measures in distributed processing models. PhD thesis, University of California, Los Angeles, 1981. 315

    Google Scholar 

  35. M. K. Molloy. Discrete Time Stochastic Petri Nets. IEEE Transactions on Software Engineering, 11:417–423, April 1985. 315

    Google Scholar 

  36. C. J. Myers and T. H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106–119, June 1993. 314

    Article  Google Scholar 

  37. S. M. Nowick and D. Dill. “Asynchronous State Machine Synthesis Using a Local Clock”. In International Workshop on Logic Synthesis, 1991. 314

    Google Scholar 

  38. S. Park and S. B. Akers. A graph theoretic approach to partial scan design by k-cycle elimination. In Proc. IEEE International Test Conference, pages 303–311, 1992. 330

    Google Scholar 

  39. J. L. Peterson. Petri Net Theory and the Modeling of Systems. Prentice Hall, 1981. 314

    Google Scholar 

  40. V. D. Ploeg. Preconditioning techniques for large sparse, non-symmetric matrices with arbitrary sparsity patterns. In Proc. IMACS Symposium on Iterative Methods in Linear Algebra, pages 173–179, 1991. 329

    Google Scholar 

  41. G. Rubino and B. Sericola. On weak lumpability in Markov chains. Journal of Applied Probability, 26:446–457, 1989. 329

    Article  MATH  MathSciNet  Google Scholar 

  42. G. Rubino and B. Sericola. Sojourn times in finite Markov process. Journal of Applied Probability, 27:744–756, 1989. 323

    Article  MathSciNet  Google Scholar 

  43. T. Shiple, R. Hojati, A. Sangiovanni-Vincentelli, and R. K. Brayton. Heuristic minimization of bdds using don’t cares. In Proc. ACM/IEEE Design Automation Conference, pages 225–231, 1994. 329

    Google Scholar 

  44. G. W. Smith, Jr. and R. B. Walford. The identification of a minimal feedback vertex set of a directed graph. IEEE Transactions on Circuits and Systems, 22(1):9–15, January 1975. 330

    Article  MathSciNet  Google Scholar 

  45. K. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 36(2):217–228, February 2001. 313

    Article  Google Scholar 

  46. G. W. Stewart. Methods of simultaneous iteration for computing invariant subspaces of non-ruminating matrices. Numerical Mathematics, 25:123–136, 1976. 329

    Article  MATH  Google Scholar 

  47. W. J. Stewart. An Introduction to the Numerical Solution of Markov Chains. Princeton University Press, 1994.

    Google Scholar 

  48. S. H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, 1969. (re-issued by R.E. Krieger, Malabar, 1983). 314

    Google Scholar 

  49. H. J. M. Veendrick. The behavior of flip-flops used as synchronizers and prediction of their falure. IEEE Journal of Solid-State Circuits, SC-15(2):169–176, April 1980. 329

    Article  Google Scholar 

  50. A. Xie and P. A. Beerel. Symbolic techniques for performance analysis of asynchronous systems based on average time separation of events. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 64–75. IEEE Computer Society Press, April 1997. 314, 318, 321, 338

    Google Scholar 

  51. A. Xie and P. A. Beerel. Efficient state classification of finite state Markov chains. IEEE Transactions on Computer-Aided Design, 17(12):1334–1338, December 1998. 314, 322, 327

    Article  Google Scholar 

  52. A. Xie and P. A. Beerel. Accelerating Markovian analysis of asynchronous systems using state compression. IEEE Transactions on Computer-Aided Design, 18(7):869–888, July 1999. 314, 327, 340

    Article  Google Scholar 

  53. A. Xie and P. A. Beerel. Performance analysis of asynchronous circuits and systems using stochastic timed Petri nets. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 239–268. Kluwer Academic Publishers, March 2000. 314

    Google Scholar 

  54. A. Xie, S. Kim, and P. A. Beerel. Bounding average time separation of events in stochastic timed Petri nets with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), April 1999. 314

    Google Scholar 

  55. Aiguo Xie. Performance Analysis of Asynchronous Circuits and Systems. PhD thesis, University of Southern California, August 1999. 321, 322, 324, 325

    Google Scholar 

  56. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, and J. Arceo. A low-controloverhead asynchronous differential equation solver. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 210–223. IEEE Computer Society Press, April 1997. 313, 334, 335

    Google Scholar 

  57. K. Y. Yun, D. L. Dill, and S. M. Nowick. Synthesis of 3D asynchronous state machines. In Proc. International Conf. Computer Design (ICCD), pages 346–350. IEEE Computer Society Press, October 1992. 314

    Google Scholar 

  58. K. Y. Yun and R. P. Donohue. Pausible clocking: A first step toward heterogeneous systems. In Proc. International Conf. Computer Design (ICCD), pages 118–123. IEEE Computer Society Press, October 1996. 336

    Google Scholar 

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Author information

Authors and Affiliations

  1. EE Department, Systems Division, University of Southern California, 90089, Los Angeles, CA

    Peter A. Beerel

  2. Fulcrum Microsystems, 91301, Calabasas Hills, CA

    Aiguo Xie

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  1. Peter A. Beerel
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  2. Aiguo Xie
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Editors and Affiliations

  1. Department of Software, Technical University of Catalonia, Campus Nord, Mòdul C5, Jordi Girona Salgado 1-3, 08034, Barcelona, Spain

    Jordi Cortadella

  2. School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle upon Tyne, NE1 7RU, UK

    Alex Yakovlev

  3. Center for Natural Computing, Leiden University, Niels Bohrweg 1, 2333, Leiden, CA, The Netherlands

    Grzegorz Rozenberg

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Beerel, P.A., Xie, A. (2002). Performance Analysis of Asynchronous Circuits Using Markov Chains. In: Cortadella, J., Yakovlev, A., Rozenberg, G. (eds) Concurrency and Hardware Design. Lecture Notes in Computer Science, vol 2549. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36190-1_9

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  • DOI: https://doi.org/10.1007/3-540-36190-1_9

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