Advertisement

Decomposition in Asynchronous Circuit Design

  • Walter Vogler
  • Ralf Wollowski
Chapter
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2549)

Abstract

Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a first step; this leads to a modular implementation, which can support circuit synthesis by possibly avoiding state explosion or allowing the use of library elements. We present a decomposition algorithm and formally prove it correct, where an interesting aspect is the use of a bisimulation with angelic nondeterminism. In contrast to similar approaches in the literature, our algorithm is very generally applicable. We show that transition contraction - the main operation in the algorithm - can be applied with fewer restrictions than known so far. We also prove that deletion of redundant places can be used in the algorithm, which turns out to be very useful in examples.

Keywords

Decomposition Algorithm Internal Transition Parallel Composition Correctness Proof Reachability Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [And83]
    C. André. Structural transformations giving B-equivalent PT-nets. In Pagnoni and Rozenberg, editors, Applications and Theory of Petri Nets, Informatik-Fachber. 66, 14–28. Springer, 1983. 154, 160, 161Google Scholar
  2. [Ber87]
    G. Berthelot. Transformations and decompositions of nets. In W. Brauer et al., editors, Petri Nets: Central Models and Their Properties, Lect. Notes Comp. Sci. 254, 359–376. Springer, 1987. 154, 165Google Scholar
  3. [BEW00]
    J. Beister, G. Eckstein, and R. Wollowski. Cascade: a tool kernel supporting a comprehensive design method for asynchronous controllers. In M. Nielsen, editor, Applications and Theory of Petri Nets 2000, Lect. Notes Comp. Sci. 1825, 445–454. Springer, 2000. 152Google Scholar
  4. [BW93]
    J. Beister and R. Wollowski. Controller implementation by communicating asynchronous sequential circuits generated from a Petri net specification of required behaviour. In G. Caucier and J. Trilhe, editors, Synthesis for Control Dominated Circuits, 103–115. Elsevier Sci. Pub. 1993. 154, 178Google Scholar
  5. [Chu86]
    T.-A. Chu. On the models for designing VLSI asynchronous digital systems. Integration: the VLSI Journal, 4:99–113, 1986. 152CrossRefGoogle Scholar
  6. [Chu87a]
    T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT, 1987. 153, 154, 155, 166, 168, 176, 178Google Scholar
  7. [Chu87b]
    T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. In IEEE Int. Conf. Computer Design ICCD’ 87, pages 220–223, 1987. 153, 154, 155, 166, 168Google Scholar
  8. [CKK+97]
    J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Information and Systems, E80-D, 3:315–325, 1997. 152Google Scholar
  9. [Dil88]
    D. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent circuits. MIT Press, Cambridge, 1988. 152, 155, 166Google Scholar
  10. [Ebe92]
    J. Ebergen. Arbiters: an exercise in specifying and decomposing asynchronously communicating components. Sci. of Computer Programming, 18:223–245, 1992. 155, 159, 166, 169zbMATHCrossRefGoogle Scholar
  11. [KGJ96]
    P. Kudva, G. Gopalakrishnan, and H. Jacobson. A technique for synthesizing distributed burst-mode circuits. In 33rd ACM/IEEE Design Automation Conf., pages 67–70, 1996. 154Google Scholar
  12. [KKT93]
    A. Kondratyev, M. Kishinevsky, and A. Taubin. Synthesis method in self-timed design. Decompositional approach. In IEEE Int. Conf. VLSI and CAD, pages 324–327, 1993. 153, 178Google Scholar
  13. [Lyn96]
    N. Lynch. Distributed Algorithms. Morgan Kaufmann Publishers, San Francisco, 1996. 152zbMATHGoogle Scholar
  14. [Pet81]
    J. L. Peterson. Petri Net Theory. Prentice-Hall, 1981. 156Google Scholar
  15. [Rei85]
    W. Reisig. Petri Nets. EATCS Monographs on Theoretical Computer Science 4. Springer, 1985. 156Google Scholar
  16. [RY85]
    L. Rosenblum and A. Yakovlev. Signal graphs: from self-timed to timed ones. In Proc. Int. Work. Timed Petri Nets, Torino, Italy, 1985. 152Google Scholar
  17. [Seg93]
    R. Segala. Quiescence, fairness, testing, and the notion of implementation. In E. Best, editor, CONCUR 93, Lect. Notes Comp. Sci. 715, 324–338. Springer, 1993. 168Google Scholar
  18. [VYC+94]
    C. Vanbekbergen, C. Ykman-Couvreur, B. Lin, and H. de Man. A generalized signal transition graph model for specification of complex interfaces. In European Design and Test Conf., pages 378–384. IEEE, 1994. 157Google Scholar
  19. [WB00]
    R. Wollowski and J. Beister. Comprehensive causal specification of asynchronous controller and arbiter behaviour. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 3–32. Kluwer Academic Publishers, 2000. 183, 189Google Scholar
  20. [Wen77]
    S. Wendt. Using Petri nets in the design process for interacting asynchronous sequential circuits. In Proc. IFAC-Symp. on Discrete Systems, Vol.2, Dresden, 130–138. 1977. 152Google Scholar
  21. [Wol97]
    R. Wollowski. Entwurfsorientierte Petrinetz-Modellierung des Schnittstellen-Sollverhaltens asynchroner Schaltwerksverbünde. PhD thesis, Uni. Kaiserslautern, FB Elektrotechnik, 1997. 154, 157Google Scholar
  22. [YKK+96]
    A. Yakovlev, M. Kishinevsky, A. Kondratyev, L. Lavagno, and M. Pietkiewicz-Koutny. On the models for asynchronous circuit behaviour with or causality. Formal Methods in System Design, 9:189–233, 1996. 183, 189CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Walter Vogler
    • 1
  • Ralf Wollowski
    • 2
  1. 1.Institut für InformatikUniversität AugsburgGermany
  2. 2.FB Elektro- und InformationstechnikUniversität KaiserlauternGermany

Personalised recommendations