Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor
This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment. Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team. The team adopted a combination of standard, “classic” techniques and methodologies, as well as some new innovative approaches. This mixture of old and new led to a well-balanced, robust verification flow which enabled finding the majority of the design problems (bugs) early in the pre-silicon stage of the project. This paper discusses an internal tool (Sniper) (patent pending) which increases the processor bus activity in a way which would uncover subtle coherency problems.
- 1.Heald R. et al “A 3rd generation Sparc V9 64-b Microprocessor” IEEE JSSC, pp. 1526–1538, Nov. 2000Google Scholar
- 2.Lauterbach G. et al “UltraSPARC-III: a 3rd generation 64b SPARC Microprocessor”, ISSCC Digest of Technical Papers, pp 410–411, Feb. 2000.Google Scholar
- 3.Heald R et al, “Implementation of a 3rd Generation SPARC V9 64b Microprocessor”, ISSCC Digest of Technical Papers, pp 412–413, Feb. 2000Google Scholar
- 4.Normoyle K. “Introducing the UltraSPARC(TM)-IIIi Microprocessor”, Microprocessor Forum, Oct. 2001Google Scholar
- 5.George Konstadinidis et al, “Implementation of a Third generation 1.1 64b Microprocessor”, ISSCC 2002.Google Scholar