Abstract
The latest improvements in the technology of digital devices allow designers to build whole systems on a single silicon chip. New problems arise in this context, one of them being the complexity of interconnections. Optimizing interfaces has become a tedious design step. Other problematic issues are global clock signal distribution and design composability, for which asynchronous design methodology proves to be a good solution. Formal methods can be used to verify the logical correctness of digital hardware. These methods are well-featured for asynchronous designs. This study introduces asynchronous bus modeling aspects in the formal framework of Action Systems.
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References
ARM Limited. AMBA Specification (Rev 2.0), 1999.
R. J. R. Back and J. von Wright. Refinement calculus: A Systematic Introduction. Springer. April 1998.
W. J. Bainbridge. Asynchronous System-on-Chip Interconnect. PhD. Thesis, University of Manchester, UK, 2000.
W. J. Bainbridge and S. B. Furber. Asynchronous Macrocell Interconnect Using MARBLE. In Proceedings of the 4 th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC’ 98) San Diego, CA, March 30–April 2, 1998.
E. W. Dijkstra. A Discipline of Programming. Prentice-Hall International, 1976.
J. Hooman. Verifying Part of the ACCESS.bus Protocol using PVS. Proceedings 15th Conference on the Foundations of Software Technology and Theoretical Computer Science, LNCS 1026, Springer-Verlag, pages 96–110, 1995.
A. Mokkedem, R. Hosabettu, M. D. Jones, G. Gopalakrishnan, Formalization and proof of a solution to the PCI 2.1 bus transaction ordering problem. Formal Methods in Systems Design, vol. 16, no. 1, pp. 93–119, January 2000.
J. Plosila. Self-Timed Circuit Design-The Action Systems Approach. Ph.D. Thesis, University of Turku, Dept of Applied Physics, Turku, Finland, 1999.
C. Purtell-Tappen. Platform Express to Accelerate Platform-Based System-on-Chip Design and Verification. ECN Magazine, September 2001.
T. Seceleanu. Systematic Design of Synchronous Digital Circuits. Ph.D. Thesis, Abo Akademi, Turku, Finland, 2001.
T. Seceleanu, J. Plosila. Hierarchical Action Systems. Manuscript. To appear as Technical Report.
A. Zitouni et al. Design of an Asynchronous VME bus Controller for Heterogeneous systems. Dedicated Systems Magazine-2000 Q3 (http://www.dedicated-systems,com).
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Plosila, J., Seceleanu, T. (2002). Specification of an Asynchronous On-chip Bus. In: George, C., Miao, H. (eds) Formal Methods and Software Engineering. ICFEM 2002. Lecture Notes in Computer Science, vol 2495. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36103-0_39
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DOI: https://doi.org/10.1007/3-540-36103-0_39
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