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A Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection

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Dependable Computing EDCC-4 (EDCC 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2485))

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Abstract

Fault injection has become a valuable methodology for dependability evaluation of computer systems. Software implemented fault injection is used because of the relative simplicity of injecting faults. In this paper we present a methodology for assessment of the error detection mechanisms of the Time-Triggered Architecture (TTA) bus structure by emulating hardware faults using software implemented fault injection. The TTA is an architecture for distributed embedded safety-critical realtime applications which have high dependability requirements. At the core of the architecture is the time-triggered communication protocol TTP/C running on a dedicated communication controller. In the TTA fail-silence is a main concern, thus high error detection coverage with small error detection latency is required. Temporal intrusiveness of the software fault injector is measured and analyzed. A fault injection tool set for use in experimental assessment of newer chip implementations of the TTPC communication controller, is developed.

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References

  1. A. Ademaj. SOS Failures in the TTA Bus Topology. Technical Report 40/2001, Vienna University of Technology, Real-Time Systems Group, Vienna, Austria, 2001.

    Google Scholar 

  2. A. Ademaj and G. Bauer. A Note on the Implementation of the Clock Synchronization Algorithm. Technical Report 44/2001, Vienna University of Technology, Real-Time Systems Group, Vienna, Austria, 2001.

    Google Scholar 

  3. Buchner at al. Characterization Of Single-Event Upsets In A Flash Analog-To-Digital Converter (AD9058). Transactions on Nuclear Science,, 47(6), Dec 2000.

    Google Scholar 

  4. G. Bauer, H. Kopetz, and W. Steiner. The Central Guardian Approach to Enforce Fault Isolation in a Time-Triggered System. Research Report 20/2002, Vienna University of Technology, Real-Time Systems Group, Vienna, Austria, 2002.

    Google Scholar 

  5. Dodd et al. Single-Event Upset And Snapback In Silicon-On-Insulator Devices and Integrated Circuits. IEEE Transactions on Nuclear Science, 47(6), Dec 2000.

    Google Scholar 

  6. E. Fuchs. An Evaluation of the Error Detection Mechanisms in MARS using Software-Implemented Fault Injection. In Second European Dependable Computing Conference (EDCC-2), Taormina, Italy, October 1996.

    Google Scholar 

  7. N. A. Kanawati G. A. Kanawati and J. A. Abraham. FERRARI: A Tool for the Validation of System Dependability Properties. In Proc. 22rh Symp. on Fault-Tolerant Computing (FTCS-22), Boston, Massachusetts, 1992.

    Google Scholar 

  8. Z. Segall J. Barton, E. Czeck and D. Siewiorek. Fault Injection Experiments using FIAT. In Transactions on Comp, volume 39, 1990.

    Google Scholar 

  9. M. Z. Rela J. C. Cunha and J. G. Silva. Can Software Implemented Fault-Injection be Used on Real-Time Systems? In Proc. 3rd European Dependable Computing Conference (EDCC-3), pages 209–226, Prague, Czech Republic, 1999.

    Google Scholar 

  10. H. Madeira J. Carreira and J. G. Silva. Xception: Software Fault Injection and Monitoring in Processor Functional Units. In IEEE Transactions on Software Engineering, volume 24 of 2, Feb 1998.

    Google Scholar 

  11. J. Arlat Y. Crouzet G. Leber J. Karlsson, P. Folkesson and J. Reisinger. Application of Three Physical Fault Injection Techniques to the Experimental Assessment of the MARS Architecture. Proc. 5th IFIP Working Conf. on Dependable Computing for Critical Applications, DCCA-5, Urbana-Champaign, IL, USA, September 1995.

    Google Scholar 

  12. H. Kopetz. TTP/C Protocol-Version 0.5. TTTech Computertechnik AG. Available at http://www.ttpforum.org.

  13. H. Kopetz. A Comparison of TTP/C and FlexRay. Technical Report 10/2001, Vienna University of Technology, Real-Time Systems Group, Vienna, Austria, 2001.

    Google Scholar 

  14. R. Shostak M. Pease and L. Lamport. Reaching Agreement in the Presence of Faults. Journal of ACM, (27(2)):228–234, 1980.

    Article  MATH  MathSciNet  Google Scholar 

  15. NASA-JPL. Single Upset Event-Galileo Project http://www.jpl.nasa.gov/galileo/messenger/oldmess/SEU.html.

  16. J. Rushby. Bus Architectures For Safety-Critical Embedded Systems. EMSOFT 2001: First Workshop on Embedded Software, 47(6), Ocrober 2001.

    Google Scholar 

  17. Beth Schroeder. On-line Monitoring: A Tutorial. IEEE Computer Magazine, (28), June 1995.

    Google Scholar 

  18. TTP/C-C1 Communications Controller Data Sheet. TTTech Computertechnik AG. Available at http://www.ttech.com.

  19. TTP/C-C2 Communications Controller Data Sheet. TTTech Computertechnik AG. Available at http://www.ttech.com.

  20. A. Steininger and C. Temple. Economic Online Self-Test In The Time-Triggered Architecture. IEEE Design & Test of Computers, 16(3):81–89, 1999.

    Article  Google Scholar 

  21. C. Temple. Avoiding The Babbling-Idiot Failure In A Time-Triggered Communication System. In 28th Annual International Symposium on Fault-Tolerant Computing, volume FTCS-28, 1998.

    Google Scholar 

  22. Time-Triggered Architecture. http://www.vmars.tuwien.ac.at/projects/tta/.

  23. Ravishankar K. Iyer Wei-Lun Kao and Dong Tang. FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults. In Dependable IEEE Transactions on Software Engineering, volume 19, Nov 1993.

    Google Scholar 

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Ademaj, A. (2002). A Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection. In: Bondavalli, A., Thevenod-Fosse, P. (eds) Dependable Computing EDCC-4. EDCC 2002. Lecture Notes in Computer Science, vol 2485. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36080-8_17

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  • DOI: https://doi.org/10.1007/3-540-36080-8_17

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00012-9

  • Online ISBN: 978-3-540-36080-3

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