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Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors

  • Huiyang Zhou
  • Matthew D. Jennings
  • Thomas M. Conte
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2624)

Abstract

Global scheduling in a treegion framework has been proposed to exploit instruction level parallelism (ILP) at compile time. A treegion is a single-entry / multiple-exit global scheduling scope that consists of basic blocks with control-flow forming a tree. Because a treegion scope is nonlinear (includes multiple paths) it is distinguished from linear scopes such as traces or superblocks. Treegion scheduling has the capability of speeding up all possible paths within the scheduling scope. This paper presents a new global scheduling algorithm using treegions called Tree Traversal Scheduling (TTS). Efficient, incremental data-flow analysis in support of TTS is also presented. Performance results are compared to the scheduling of the linear regions that result from the decomposition of treegions. We refer to these resultant linear regions as linear treegions (LT) and consider them analogous to superblocks with the same amount of code expansion as the base treegion. Experimental results for TTS scheduling show a 35% speedup compared to basic block (BB) scheduling and a 4% speedup compared to LT scheduling.

Keywords

Basic Block Control Flow Graph Global Schedule Branch Prediction Branch Instruction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    W.A. Havanki, S. Banerjia, and T. M. Conte. “Treegion scheduling for wide-issue processors.” Proc. of the 4 th Symp. on High-Perf. Comp. Arch. (HPCA-4), February 1998.Google Scholar
  2. 2.
    S. Banerjia, W. A. Havanki, and T. M. Conte. “Treegion scheduling for highly parallel processors.” Proceeding of Euro-Par’97, August, 1997.Google Scholar
  3. 3.
    W.W. Hwu, S.A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Riyohara, G. E. Haab, J. G. Holm, and D. M. Lavery. “The Superblock: An effective way for VLIW and superblock compilation.” The Journal of Supercomputing, vol. 7, pp. 229–248, January 1993.Google Scholar
  4. 4.
    J. A. Fisher. “Trace scheduling: A technique for global microcode compaction.” IEEE Trans. Computer, vol. C-30, no. 7, pp. 478–490, July 1981.CrossRefGoogle Scholar
  5. 5.
    J. A. Fisher, “Global code generation for instruction level parallelism: Trace Scheduling-2,” Tech. Rep. HPL-93-43, Hewlett-Packard Laboratories, June 1993.Google Scholar
  6. 6.
    B. L. Deitrich and W. W. Hwu. “Speculative hedge: regulating compile-tim speculation against profile variations.” Proc. 29 th Int’l Symp. Microarchitecture (MICRO29), 1996.Google Scholar
  7. 7.
    V. Kathail, M. S. Schlansker, and B. R. Rau, “HPL PlayDoh architecture specification: version 1.0.” Tech. Rep. HPL-93-80, Hewlett-Packard Laboratories, February 1994.Google Scholar
  8. 8.
    V. Kathail, M. S. Schlansker, and B. R. Rau, “HPL-PD architecture specification: version 1.1.” Tech. Rep. HPL-93-80 (R.1), Hewlett—Packard Laboratories, February 2000.Google Scholar
  9. 9.
    S. A. Mahlke, “Exploiting instruction level parallelism in the presence of branches.” PhD thesis, Dept. of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, 1996.Google Scholar
  10. 10.
    S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann “Effective compiler support for predicated execution using the Hyperblock” Proc. 25 th Ann. Int’l Symp. Microarchitecture (MICRO25), December, 1992.Google Scholar
  11. 11.
    P. Y. T. Hsu and E. S. Davison, “Highly concurrent scalar processing”, Proc. 13 th Ann. Int’l Symp. Computer Architecture (ISCA-13), June 1986.Google Scholar
  12. 12.
    S. M. Moon and K. Ebcioğlu. “An efficient resource-constrained global scheduling technique for superscalar and VLIW processors.” Proc. 25 th Ann. Int’l Symp. Microarchitecture (MICRO25), December, 1992.Google Scholar
  13. 13.
    A. Nicolau. “Percolation scheduling: a parallel compilation technique.” Tech. Rep. TR-85-678, Department of Computer Science, Cornell University, May 1985.Google Scholar
  14. 14.
    The LEGO Compiler. Available for download at http://www.tinker.ncsu.edu/LEGO
  15. 15.
    K. N. Menezes, S. W. Sathaye, and T. M. Conte. “Path Prediction for high issue-rate processors.” Conf. On Parallel Arch. and Compilation Techniques (PACT’97), 1997.Google Scholar
  16. 16.
    J. Hoogerbrugge. “Dynamic branch prediction for a VLIW processor.” Proc. Of the 2000 Conf. On Parallel Architectures and Compilation Techniques (PACT’00), October, 2000.Google Scholar
  17. 17.
    J. Bharadwaj, K. Menezes, and C. McKinsey. “Wavefront scheduling: Path based data representation and scheduling of subgraphs.” Proc. 32 nd Ann. Int’l Symp. Microarchitecture (MICRO32), December, 1999.Google Scholar
  18. 18.
    A. V. Aho, R. Sethis, and J. D. Ullman “Compilers Principles, Techniques, and Tools.” Addison-Wesley Publishing Company, March, 1988.Google Scholar
  19. 19.
    T. M. Conte, S. Banerjia, S. Y. Larin, K. N. Menezes, and S. W. Sathaye, “Instruction fetch mechanisms for VLIW architectures with compressed encodings.” Proc. 29 th Ann. Int’l Symp. Microarchitecture (MICRO29), December, 1996.Google Scholar
  20. 20.
    S. Aditya, V. Kathail, and B. R. Rau, “Elcor’s machine description system: version 3.0.” Tech. Rep. HPL-98-128 (R.1), Hewlett—Packard Laboratories, October 1998.Google Scholar
  21. 21.
    M. S. Schlansker and B. R. Rau. “EPIC: Explicitly Parallel Instruction Comupting.” IEEE Computer, Vol. 33, Issue 2, February 2000.Google Scholar
  22. 22.
    M. D. Smith. “Architectural support for compile-time speculation.” In D. Lilja and P. Birds, editors. The Interaction of Compilation Technology and Computer Architecture. Kluwer Academic Publishers, Boston, 1994.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Huiyang Zhou
    • 1
  • Matthew D. Jennings
    • 1
  • Thomas M. Conte
    • 1
  1. 1.Department of Electrical and Computer EngineeringNorth Carolina State UniversityUSA

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