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Packaging Challenges in Miniaturization

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Abstract

Classically, packaging consists of assembly, interconnection and passivation. The technological advances in miniaturization, however, have changed all three aspects and have moved the focus onto system integration. Instead of developing hardware, software and technology separately, the whole system has to be considered and optimized for a further size reduction. The following chapter discusses the design and realization of tiny, highly integrated devices. It will show interdependenc es between the miniaturization techniques as well as the design of hardware and software. Initially several system aspects will be mentioned. Thereafter the integration technologies will be reflected in more detail.

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References

  1. C. Landesberger et al. “New Dicing and Thinning Concept Improves Mechanical Reliability of Ultra Thin Silicon”, Int. Symp. and Exhibition on Materials, Braselton, Georgia, March 2001.

    Google Scholar 

  2. S. Nieland et al., “Immersion Soldering — a New Way for Ultra Fine Pitch Bumping”, Proc. of Electronic Goes Green 2000 Conference, Berlin, Germany, 2000, pp. 165–167.

    Google Scholar 

  3. B. Pahl et al., “A Thermode Bonding Process for Fine Pitch Flip Chip Applications Down to 40 Micron”, Proc. EMAP, Korea, 2001.

    Google Scholar 

  4. R. Aschenbrenner et al., “Evaluation of Adhesive Flip Chip Bonding on Flexible Substrates”, Proc. Flexcon’ 97, Sunnyvale, 1997.

    Google Scholar 

  5. Alien technology corporation: Fluidic self assembly; www.alientechnology.com/mambo_alien/library/pdf/fsa_white_paper.pdf.

    Google Scholar 

  6. C. Kallmayer et al., “New Assembly Technologies for Textile Transponder Systems”, Proc. 53rd ECTC, New Orleans, 2003.

    Google Scholar 

  7. R. Filion, R. Wojnarowski, T. Gorcyzca, B. Wildi, H. Cole; “Development of a Plastic Encapsulated Multichip Technology for High Volume, Low Cost Commercial Electronics”, 10. Applied Power Electronics Conf, IEEE, 1994, pp. 805–809.

    Google Scholar 

  8. Owzar, K. Buschik, O. Ehrmann; M. Kasper; “RF-Investigation of the electrical parameters of the embedded chip structure”, Proc. VLSI Packaging Workshop, Monterey USA, October 16–18, (1995).

    Google Scholar 

  9. T. Waris, R. Tuominen, J. Kivilahti, “Panel-sized Integrated Module Board Manufacturing”, Proc. Polytronic Conference, Oct. 21–24. 2001, Potsdam, Germany.

    Google Scholar 

  10. R. Tuominen, P. Palm, “Development of industrial scale manufacturing line for Integrated Module Board technology”, 6th VLSI Packaging Workshop of Japan, November 12–14., 2002, Kyoto.

    Google Scholar 

  11. H. Braunisch, S. Towle, R. Emery, C. Hu and G. Vandentop, “Electrical Performance of Bumpless Build-Up Layer Packaging”, Proc. ECTC 2002, May 28–31. 2002, San Diego, USA.

    Google Scholar 

  12. A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Böttcher and H. Reichl, “Realization of a Stackable Package Using Chip in Polymer Technology”, Polytronic Conference, June 23–26. 2002, Zalaegerszeg, Hungary.

    Google Scholar 

  13. A. Ostmann, A. Neumann, J. Auersperg, C. Ghahremani, G. Sommer, R. Aschenbrenner and H. Reichl, “Integration of Passive and Active Components into Build-Up Layers”, EPTC 2002.

    Google Scholar 

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© 2005 Springer-Verlag Berlin Heidelberg

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Kallmayer, C., Niedermayer, M., Guttowski, S., Reichl, H. (2005). Packaging Challenges in Miniaturization. In: Weber, W., Rabaey, J.M., Aarts, E. (eds) Ambient Intelligence. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-27139-2_15

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  • DOI: https://doi.org/10.1007/3-540-27139-2_15

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23867-6

  • Online ISBN: 978-3-540-27139-0

  • eBook Packages: EngineeringEngineering (R0)

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