This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Bibliography
H. Arakawa, “Address Decoder Circuit for Non-Volatile Memory”, United States Patents 5,039,882, Aug 13, (1991).
S. Atsumi, A. Umezawa, M. Kuriyama, H. Banba, N. Ohtsuka, N. Tomita, Y. Iyama, T. Miyaba, R. Sudoh, E. Kamiya, M. Tanimoto, Y. Hiura, Y. Araki, E. Sagakami, N. Arai, and S. Mori, “A 3.3V-only 16Mb flash memory with row-decoding scheme”, 1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 42–43, (Feb. 1996).
G. Campardo, R. Micheloni, S. Commodaro, “Line decoder for memory devices”, USA Patent No. 6,018,255, (January 25, 2000).
G. Campardo, R. Micheloni, “Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector”, USA Patent No. 6,122,200, (September 19, 2000).
G. Campardo et al., “Circuit structure for providing a hierarchical decoding in semiconductor memory devices”, USA patent No. 6,515,911, (February 4, 2003).
J. C. Chen et al., A 2.7V Only 8Mx16 NOR Flash Memory, Symposium on VLSI Circuits, Digest of Technical Papers, IEEE, (1996).
Kobayashi el al., “A 3.3V-Only 16 MB DINOR Flash Memory”, FLASH MEMORY SESSION, ISSCC95.
R. Micheloni, et al., “Row decoder circuit for an electronic memory device, particularly for low voltage applications”, USA patent No. 6,069,837, (May 30, 2000).
R. Micheloni et al., “Line decoder for a low supply voltage memory device”, USA patent No. 6,111,809, (August 29, 2000).
R. Micheloni et al., “Nonvolatile memory device, in particular a flash-EEPROM”, USA patent No. 6,351,413, (February 26, 2002).
Y. Miyawaki et al., “A New Erasing and Row decoding scheme for low supply voltage operation 16-Mb/64-Mb Flash Memories”, IEEE Journal of Solid State Circuits, Vol. 27, N 4, (April 1992).
A. Umezawa et al., “A 5V-Only operation 0.6um Flash EEPROM with Row decoder scheme in triple-well structure”, IEEE Journal of Solid State Circuits, Vol. 27, N 11, (November 1992).
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
(2005). Decoders. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_9
Download citation
DOI: https://doi.org/10.1007/3-540-26500-7_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20198-4
Online ISBN: 978-3-540-26500-9
eBook Packages: EngineeringEngineering (R0)