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From Specification Analysis to Floorplan Definition

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VLSI-Design of Non-Volatile Memories
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Bibliography

  • B. Venkatesh et al., “A 55ns 0.35um 5V-Only 16M Flash Memory with Deep-Power-Down”, ISSCC96.

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  • R. Micheloni, M. Zammattio, G. Campardo, O. Khouri, and G. Torelli, “Hierarchical sector biasing organization for Flash memories”, in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 29–33, (Aug. 2000).

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© 2005 Springer-Verlag Berlin Heidelberg

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(2005). From Specification Analysis to Floorplan Definition. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_22

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  • DOI: https://doi.org/10.1007/3-540-26500-7_22

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20198-4

  • Online ISBN: 978-3-540-26500-9

  • eBook Packages: EngineeringEngineering (R0)

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