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Bibliography

  • B.T. Ahlport et al., “CMOS?SOS LSI input/output protection networks”, IEEE Transactions on Electron Devices, Vol. ED-25, No. 8, pp. 933–938, (August 1978).

    Google Scholar 

  • S. H. Cohen, G. Caswell, “An improved input protection circuit for CMOS/SOS ARRAY”, IEEE Transactions on Electron Devices, Vol. ED-25, No. 8, pp. 926–932, (August 1978).

    Google Scholar 

  • C. Duvvury, et al., “A Synthesis of ESD input protection scheme”, EOS/ESD Symposium Proccedings, pp. 88–98, (1991).

    Google Scholar 

  • C. Duvvury, et al., “Dymanic gate coupling of NMOS for efficient output ESD protection”, IEEE, IRPS, pp. 141–150, (1992).

    Google Scholar 

  • W.S. Feng, et al., “MOSFET drain breakdown voltage”, IEEE Electron Device Letters, Vol. EDL-7, No. 7, pp. 449–450, (July 1986).

    Google Scholar 

  • E. Fujishi, et al., “Optimized ESD protection circuits for high speed CMOS/VLSI”, Custom Integrated Circuits Conference, pp. 569–573, (1984).

    Google Scholar 

  • F.C. Hsu, R.S. Muller, C. Hu, “A simplified Model of short channel MOSFET characteristics in the breakdown mode”, IEEE Transactions on Electrical Devices, Vol. ED-30, No. 6, pp. 571–576, (June 1983).

    Google Scholar 

  • G.J. Hu, “A better understanding of CMOS latch-up”, IEEE Transaction on Electron Devices, Vol. ED-31, No. 1, pp. 62–67, (January 1984).

    Google Scholar 

  • G. Krieger, “Nonuniform ESD current distribution due to improper metal routing”, EOS/ESD Symposium Proccedings, pp. 104–109, (1991).

    Google Scholar 

  • I.M. Mackintosh, “The electrical characteristichs of silicon P-N-P-N Triodes”, Proceeding of the IRE, pp. 1229–1235, (June 1958).

    Google Scholar 

  • T.J. Maloney, “Designing MOS inputs and outputs to avoid oxide failure in the charged device model”, EOS/ESD Symposium Proccedings, pp. 220–227, (1988).

    Google Scholar 

  • P.S. Neelakan Taswany,”MOS scaling effects on ESD-based failure”, IEEE Custom Integrated Circuits Conference, pp. 400–403, (1986).

    Google Scholar 

  • Troutman, Latch-up in CMOS Technology The problem and Its Cure, Kluwer Academic Publishers, (1986).

    Google Scholar 

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© 2005 Springer-Verlag Berlin Heidelberg

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(2005). ESD & Latch-Up. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_21

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  • DOI: https://doi.org/10.1007/3-540-26500-7_21

  • Publisher Name: Springer, Berlin, Heidelberg

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