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Bibliography
B. Benjauthrit, L. Coday, and M. Trcka, “An overview of error control codes for data storage,” in 1996 IEEE Int. Non-Volatile Memory Technology Conf., pp. 120–126, (1996).
J.M. Berger, “A note on error detection codes for asymmetric channels”, Information and Control, no. 4, pp. 68–73, (1961).
R.E. Blahut, Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley Publishing Company, (1983).
C.L. Chen, “Symbol error correcting codes for computer memory systems,” IEEE Trans. Comput., vol. 41, no. 2, pp. 252–256, (Feb. 1992).
C.L. Chen, “Symbol error correcting codes for memory applications,” in Proc. Annual Symposium on Fault Tolerant Computing, pp. 200–207, (1996).
C.L. Chen, “Some results on symbol error-correcting codes,” in Proc. 2000 IEEE Int. Symp. on Information Theory, p. 475, (2000).
C.L. Chen, M.Y. Hsiao, “Error-correcting codes for semiconductor memory applications: a state-of-the-art review,” IBM J. Res. Develop., vol. 28, no. 2, pp. 124–134, (Mar. 1984).
T. Cho, Y.-T. Lee, E.-C. Kim, J.-W. Lee, S. Choi, S. Lee, D.-H. Kim, W.-G. Han, Y.-H. Lim, J.-D. Lee, J.-D. Choi, and K.-D. Suh. “A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes,” IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1700–1706, (Nov. 2001).
D.J. Costello, Jr., J. Hagenauer, H. Imai, and S. B. Wicker, “Applications of error-control coding,” IEEE Trans. Inform. Theory, vol. 44, no. 6, pp. 2531–2560, (Oct. 1998).
J. Cunningham, ”The use and evaluation of yield models in integrated circuit manufacturing”, IEEE J. Solid-State Circuits, vol. 3, pp. 60–71, (May. 1990).
J.A. Fifield and C.H. Stapper, “High-speed on-chip ECC for synergistic fault-tolerant memory chips,” IEEE J. Solid-State Circuits, vol. 26, no. 10, pp. 1449–1452, (Oct. 1991).
H.L. Davis, “A 70-ns word-wide 1-Mbit ROM with on-chip error-correction circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 958–963, (Oct. 1985).
T. Fuja, C. Heegard, and R. Goodman, “Linear sum codes for random access memories,” IEEE Trans. Comput., vol. 37, no. 9, pp. 1030–1042, (Sept. 1988).
K. Furutani, K. Arimoto, H. Miyamoto, T. Kobayashi, K. Yasuda, and K. Mashiko, “A built-in Hamming code ECC circuit for DRAM’s,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 50–56, (Feb. 1989).
R.M. Goodman, “On-chip ECC for multi-level random access memories,” in Proc. 1989 IEEE/CAM Information Theory Workshop, pp. 7–4, (1989).
R.M. Goodman, M. Sayano, “The reliability of semiconductor RAM memories with on-chip error-correction coding,” IEEE Trans. Inform. Theory, vol. 37, no. 3, pp. 884–896, (May 1991).
S. Gregori, P. Ferrari, R. Micheloni, and G. Torelli, “Construction of polyvalent error control codes for multilevel memories”, in Proc. 7th IEEE International Conference on Electronics, Circuits, and Systems, pp. 751–754, (Dec. 2000).
S. Gregori, O. Khouri, R. Micheloni, and G. Torelli, “An error control code scheme for multilevel Flash memories,” in Records 2001 IEEE International Workshop on Memory Technology, Design and Testing, pp. 45–49, (Aug. 2001).
S. Gregori, et al., “On-Chip error correcting technique for new generation Flash memories”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 602–616, (April 2003).
R.W. Hamming, “Error detecting and error correcting codes,” Bell Syst. Tech. J., vol. 26, pp. 147–150, (1950).
A. Hocquenghem, “Error corrector codes” (Codes correcteurs d’erreurs), Chiffres, no. 2, pp. 147–156, (1959).
H.L. Kalter, C.H. Stapper, J.E. Barth, Jr., J. DiLorenzo, C.E. Drake, J.A. Fifield, G.A. Kelley, Jr., S.C. Lewis, W.B. van der Hoeven, and J.A. Jankoski, “A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC,” IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1118–1128, (Oct. 1990).
M. Kubo and S. Chou, “Fault tolerant techniques for memory components,” in 1985 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 230–231, (Feb. 1985).
P. Mazumder, “An on-chip ECC circuit for correcting soft errors in DRAM’s with trench capacitors,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1623–1633, (Nov. 1992).
T. Michalka et al., ”A discussion of yield modeling with defect clustering,circuit repair and circuit redundancy”, IEEE J. Solid-State Circuits, vol. 3,pp. 116–127, (Aug. 1990).
T. Nakayama, Y. Miyawaki, K. Kobayashi, Y. Terada, H. Arima, T. Matsukawa, and T. Yoshihara, “A 5-V-only one-transistor 256K EEPROM with page-mode erase,” IEEE J. Solid-State Circuits, vol. 24, no. 4, pp. 911–915, (Aug. 1989).
W.W. Peterson and E. J. Weldon, Jr., Error Correcting Codes, 2nd ed. Cambridge, MA: M.I.T. Press, (1972).
F.I. Osman, “Error-correction technique for random-access memories,” IEEE J. Solid-State Circuits, vol. 17, no. 5, pp. 877–882, (Oct. 1982).
B. Polianskikh and Z. Zilic, “Design and implementation of error detection and correction circuitry for multilevel memory protection,” in Proc. 32nd IEEE Int. Symp. on Multiple-Valued Logic, pp. 89–95, (2002).
T.R.N. Raho and E. Fujiwara, Error Control Coding for Computer Systems. Englewood Cliffs, NJ: Prentice Hall, (1989).
P. Ramanathan, K. K. Saluja, and M. Franklin, “Testing check bits at no cost in RAMs with on-chip ECC,” IEE Proceedings-E, vol. 140, no. 6, pp. 304–312, (Nov. 1993).
D. Rossi, C. Metra, and B. Riccò, “Fast and compact error correcting scheme for reliable multilevel Flash memory,” in Proc. 2002 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 27–31, (2002).
C.V. Srinivasan, “Codes for error correction in high-speed memory systems — part I: correction of cell defects in integrated memories,” IEEE Trans. Comput., vol. 20, no. 8, pp. 882–888, Aug. (1971).
C.H. Stapper and H.-S. Lee, “Synergistic fault-tolerance for memory chips,” IEEE Trans. Comput., vol. 41, no. 9, pp. 1078–1087, (Sept. 1992).
T. Tanzawa, T. Tanaka, K. Takekuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takekuchi, and K. Ohuchi, “A compact on-chip ECC for low cost Flash memories,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 662–669, (May 1997).
T. Toyabe, T. Shinoda, M. Aoki, H. Kwamoto, K. Mitsusada, T. Masuhara, and S. Asai, “A soft error rate model for MOS dynamic RAM’s,” IEEE J. Solid-State Circuits, vol. 17, no. 2, pp. 362–367, (Apr. 1982).
R. Vancu, L. Chen, R. L. Wan, T. Nguyen, C.-Y. Yang, W.-P. Lai, K.-F. Tang, A. Mihnea, A. Renninger, and G. Smarandoiu, “A 35ns 256k CMOS EEPROM with error correcting circuitry,” in 1990 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 64–65, (Feb. 1990).
J. Yamada, “Selector-line merged built-in ECC technique for DRAM’s,” IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 868–873, (Oct. 1987).
T. Yamada et al., ”A 4-Mbit DRAM with 16-bit concurrent ECC”, IEEE J. Solid-State Circuits, vol. SC-23, pp. 20–25, (Feb. 1988).
G.-C. Yang, “Reliability of semiconductor RAMs with soft-error scrubbing techniques,” IEE Proc. — Comput. Digit. Tech., vol. 142, no. 5, pp. 337–344, (Sept. 1995).
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(2005). Redundancy and Error Correction Codes. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_18
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