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Circuits Used in Program and Erase Operations

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VLSI-Design of Non-Volatile Memories
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Bibliography

  • B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, Journal of Solid-State Circuits, vol. SC-18, pp. 629–633, (Nov. 1983).

    MathSciNet  Google Scholar 

  • P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston

    Google Scholar 

  • C. S. Bill el al., High Voltage charge pumps with series capacitances, U.S. patent No. 5,059,815, (Oct. 22, 1991).

    Google Scholar 

  • G. Di Cataldo and G. Palumbo, “Double and triple charge pump for power IC dynamic models which take parasitic effects into account”, IEEE Trans. Circuits Syst., vol. CAS-40, pp. 92–101, (Feb. 1993).

    Google Scholar 

  • J. Dickson, “On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique”, IEEE J. Solid-State Circuits, vol. SC-11, no. 3, pp. 374–378, (Jun. 1976).

    Google Scholar 

  • P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler”, IEEE J. Solid State Circuits, vol. SC-33, pp. 410–416, (Mar. 1998).

    Google Scholar 

  • A. Ghilardelli, G. Campardo, J. Mulatti, “Bidirectional charge pump generating either a positive or negative voltage”, USA patent No. 6,184,741, (Feb. 6, 2001).

    Google Scholar 

  • P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits. New York, NY: Kluwer John Wiley & Sons, Inc., ch. 4, (2001).

    Google Scholar 

  • S.S. Haddadi et al., Flash E2PROM Array with Negative Gate Voltage Erase Operation, U.S. patent n. 5,077,691, (Oct. 23, 1989).

    Google Scholar 

  • T. Kawahama et al., Bit line clamped sensing Multiplex and accurate high voltage generator for quarter micron Flash memory, Journal of Solid State Circuit, Vol 31, No 11, p. 1590, (Nov. 96).

    Google Scholar 

  • T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, and K. Kimura, “Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25µm flash memories”, in 1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 38–39, (Feb. 1996).

    Google Scholar 

  • O. Khouri, S. Gregori, R. Micheloni, D. Soltesz, and G. Torelli, “Low output resistance charge pump for Flash memory programming”, 2001 IEEE Proc. Int. Workshop on Memory Technology, Design and Testing, San Jose, CA (USA), pp. 99–104, (Aug. 2001).

    Google Scholar 

  • O. Khouri, S. Gregori, A. Cabrini, R. Micheloni, and G. Torelli, “Improved charge pump for Flash Memory applications in triple-well CMOS technology”, in 2002 IEEE Proc. Int. Symposium on Industrial Electronics, L’Aquila (Italy), pp. 1322–1326, (Jul. 2002).

    Google Scholar 

  • O. Khouri, R. Micheloni, and G. Torelli, “Very fast recovery word-line voltage regulator for multilevel non-volatile memories”, in Proc. Third IMACS/IEEE Int. Multiconference Circuits, Communications and Computers, Athens, Greece, pp. 3781–3784, (Jun. 1999).

    Google Scholar 

  • O. Khouri, R. Micheloni, I. Motta, A. Sacco, G. Torelli, “Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories”, U.S. Patent No. 6.259.635, (Jul. 10, 2001).

    Google Scholar 

  • O. Khouri, R. Micheloni, I. Motta, A. Sacco, G. Torelli, “Capacitive compensation circuit for the regulation of the wordline reading voltage in non-volatile memories”, U.S. Patent No. 6.259.632, (Jul. 10, 2001).

    Google Scholar 

  • O. Khouri, R. Micheloni, I. Motta, and G. Torelli, “Voltage regulating circuit for a capacitive load”, U.S. Patent No. 6.249.112, (Jun. 19, 2001).

    Google Scholar 

  • O. Khouri, R. Micheloni, A. Sacco, G. Campardo, and G. Torelli, “Program word-line voltage generator for multilevel Flash memories”, in Proc. 7th IEEE Int. Conf. on Electronics, Circuits, and Systems, vol. II, pp. 1030–1033, (Dec. 2000)

    Google Scholar 

  • O. Khouri, R. Micheloni, S. Gregori, and G. Torelli, “Fast Voltage Regulator for Multilevel Flash Memories”, in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 34–38, (Aug. 2000).

    Google Scholar 

  • M. Maccarrone et al, “Program load adaptive voltage regulator for Flash memories”, Journal of Solis State Circuit, Vol. 32, No 1, p. 100, (Jan. 1997). F. Maloberti, Analog Design for CMOS VLSI Systems, 2001 Kluwer Academic Publishers, Boston

    Google Scholar 

  • M. Mihara, Y. Terada, and M. Yamada, “Negative heap pump for low voltage operation flash memory”, in 1996 Symposium VLSI Circuits Dig. Tech. Pap., pp. 76–77, (Jun. 1996).

    Google Scholar 

  • D.B. Ribner, M.A. Copeland, Design Techniques for Cascode CMOS Op Amps with Improved PSRR and Common Mode Input Range, IEEE Journal of Solid-State Circuits, vol. SC-19, N. 6, pp. 919–925, (Dec. 1984)

    Google Scholar 

  • G.A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator”, IEEE J.Solid-State Circuits, vol. SC-33, pp. 36–44, (Jan. 1998).

    Google Scholar 

  • T. Tanzawa and T. Tanaka, “A dynamic analysis of the Dickson charge pump circuit”, IEEE J. Solid-State Circuits, vol. SC-32, no. 8, pp. 1231–1240, ( Aug. 1997).

    Google Scholar 

  • J.S. Witters, G. Groeseneken, and H. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits”, IEEE.J. Solid-State Circuits, vol. SC-24, pp. 1372–1380, (Oct. 1989).

    Google Scholar 

  • C.C Wang and J. Wu, “Efficiency improvement in charge pump circuits”, IEEE J. Solid-State Circuits, vol. SC-32, pp. 852–860, (Jun. 1997).

    Google Scholar 

  • R.J. Widlar, “New developments in IC voltage regulators”, IEEE J. Solid-State Circuits, vol. SC-20, pp. 816–818, (Feb. 1971).

    Google Scholar 

  • J.T. Wu and K.L. Chang, “MOS charge pumps for low-voltage operation”, IEEE J. Solid-State Circuits, vol. 33, pp.592–597, (Apr. 1998).

    Article  Google Scholar 

  • M. Zhang. N. Llaser, and F. Devos, “Improved voltage tripler structure with symmetrical stacking charge pump”, El. Letters, vol. 37, pp. 668–669, (May 2001).

    Google Scholar 

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(2005). Circuits Used in Program and Erase Operations. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_15

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  • DOI: https://doi.org/10.1007/3-540-26500-7_15

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  • Print ISBN: 978-3-540-20198-4

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