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Bibliography
M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, and K. Wojciechowski,, “A multilevel-cell 32Mb Flash memory”, in 1995 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 132–133, (Feb. 1995).
G. Campardo et al., “40mm2 3V Only 50 MHz 64 Mb 2-b/cell CHE NOR Flash Memory”, J. of Solid State Circuits, 35, 1665, (2000).
G. Campardo and R. Micheloni “Architecture of non volatile memory with multi-bit cells” Elsevier Science, Microelectronic Engineering, Volume 59, Issue 1–4, pagg. 173–181, (November 2001).
Y.-J. Choi, K.-D. Suh, Y.-N. Koh, J.-W. Park, K.-J. Lee, Y.-J. Cho, and B.-H. Suh, “A high speed programming scheme for multi-level NAND Flash memory”, in 1996 Symp. VLSI Circuits Dig. Tech. Papers., pp. 170–171, (June 1996).
C. de Graaf, P. Young, and D. Hulsbos, “Feasibility of multilevel storage in Flash EEPROM cells”, in Proc. 25th European Solid State Device Research Conf., pp. 213–216, (Sept. 1995).
M. Grossi, et al., “Program schemes for multilevel Flash Memories”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 594–601, (April 2003).
M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, and K. Shimohigashi: “An experimental large-capacity semiconductor file memory using 16-levels/cell storage,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 27–33, (Feb. 1988).
T.S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H. Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Lee, H.-K. Lim, “A 117-mm2 3.3V only 128-Mb multilevel NAND Flash memory for mass storage applications”, IEEE J. Solid-State Circuits, vol. SC-31, pp. 1575–1583, (November 1996).
R. Micheloni, O. Khouri, S. Gregori, A. Cabrini, G. Campardo, L. Fratin, and G. Torelli, “A 0.13-µm CMOS NOR Flash memory experimental chip for 4-b/cell storage,” ESSCIRC 28th Proc. European Solid-State Circuit Conf., pp. 131–134, (Sept. 2002).
R. Micheloni, I. Motta, O. Khouri, and G. Torelli, “Stand-by low-power architecture in a 3-V only 2-bit/cell 64-Mbit Flash memory”, in Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, vol. II, pp. 929–932, (Sept. 2001).
R. Micheloni et al., “Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory”, USA patent No. 6,301,149, (October 9, 2001).
R. Micheloni et al., “Read circuit for a nonvolatile memory”, USA patent No. 6,327,184, (December 4, 200).
A. Modelli, R. Bez, A. Visconti “Multi-level Flash Memory Technology”, 2001 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Extended Abstract, pp. 516–517, (2001).
A. Modelli, A. Manstretta, and G. Torelli, "Basic Feasibility Constraints for Multilevel CHE-Programmed Flash Memories", IEEE Trans. Electron Devices, ED-48, NO. 9, pp. 2032–2042, (September 2001).
M. Ohkawa el al., “A 9.8mm2 Die size 3.3V 64Mb Flash memory with FN-NOR type Four level cell”, IEEE, Journal of Solid-State Circuit, vol. 31, no. 11, p. 1584, (Nov. 96).
B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, and A. Modelli, “Nonvolatile multilevel memories for digital applications”, Proc. IEEE, vol. 86, pp. 2399–2421, (Dec. 1998).
P. L. Rolandi, et al.: “1M-cell 6b/cell analog flash memory for digital storage”, IEEE ISSCC Dig. Tech. Papers, pp. 334–335, (Feb. 1998).
P.L. Rolandi et al., “A 32Mb-4b/cell analog Flash Memory Supporting Variable Density with Only Supply and serial I/O”, 25th ESSCIRC ’99.
R. Shirota, G.J. Hemink, K. Takeuchi, H. Nakamura, and S. Aritome, “A new programming method and cell architecture for multi-level NAND Flash memories”, presented at the 14h IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, paper 2.7, (Aug. 1995).
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(2005). Multilevel Read. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_13
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DOI: https://doi.org/10.1007/3-540-26500-7_13
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