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Design and scheduling of mesh array of hardware unifiers for large-scale unification

  • Session 8: Vlsi, Dataflow And Array Processors
  • Conference paper
  • First Online:
Supercomputing (ICS 1987)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 297))

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Abstract

We propose a hardware unification array consisting of k × n fourconnected unification units to be used to speed up the process of finding suitable bindings for common variables among the predicates in a logic program. Four different algorithms (SIMPLEX, PCC, PwFLP and CP) to perform unification in the array are presented and their performances compared. The final level of unification in scheduling multiple arrays is found to be the most expensive, deserving the highest degree of hardware support.

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References

  1. T. Moto-oka and H. Stone, "Fifth-Generation Computer Systems: a Japanese Project", IEEE Computer, (March 1984), pp. 6–13.

    Google Scholar 

  2. W.F. Clocksin and C.S. Mellish, Programming in Prolog, (1981), Springer-Verlag.

    Google Scholar 

  3. J.S. Conery and D.F. Kibler, "Parallel Interpretation of Logic Programs", Proceedings of 1981 Conference on Functional Programming Languages and Computer Architectures, (1981), pp. 163–170.

    Google Scholar 

  4. J.A. Robinson, "A Machine-Oriented Logic Based on the Resolution Principle, JACM, 12(1), pp. 23–41.

    Google Scholar 

  5. Y. Shobatake and H. Aiso, "A Unification Processor Based on Uniformly Structured Cellular Hardware", 13th Annual International Symposium on Computer Architecture, pp. 140–148.

    Google Scholar 

  6. T.P. Dobry, et. al., "Performance Studies of Prolog Machine Architectures", 12th International Symposium on Computer Architecture, pp. 180–190.

    Google Scholar 

  7. R. Nakazaki, et. al., "Design of a High Speed Prolog Machine (HPM)", 12th International Symposium on Computer Architecture, pp. 191–197.

    Google Scholar 

  8. P. Robinson, "The SUM: an AI Coprocessor", BYTE, (June, 1985), pp. 169–180.

    Google Scholar 

  9. H. Nakagawa, "AND Parallel Prolog with Divided Assertion Set", 1984 Symposium on Logic Programming, pp. 22–28.

    Google Scholar 

  10. Y.F. Shin, Parallel Processing of Production Systems: An Integrated Software and Hardware Approach, Ph.D. Dissertation, The University of Michigan, 1987.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Computing Research Laboratory Department of Electrical Engineering and Computer Science, The University of Michigan, 48109, Ann Arbor, MI

    Yifong Shih & Keki B. Irani

Authors
  1. Yifong Shih
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  2. Keki B. Irani
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Editor information

E. N. Houstis T. S. Papatheodorou C. D. Polychronopoulos

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© 1988 Springer-Verlag Berlin Heidelberg

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Shih, Y., Irani, K.B. (1988). Design and scheduling of mesh array of hardware unifiers for large-scale unification. In: Houstis, E.N., Papatheodorou, T.S., Polychronopoulos, C.D. (eds) Supercomputing. ICS 1987. Lecture Notes in Computer Science, vol 297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18991-2_39

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  • DOI: https://doi.org/10.1007/3-540-18991-2_39

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18991-6

  • Online ISBN: 978-3-540-38888-3

  • eBook Packages: Springer Book Archive

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